mirror of
https://github.com/KarolS/millfork.git
synced 2024-05-31 18:41:30 +00:00
1382 lines
26 KiB
Scala
1382 lines
26 KiB
Scala
package millfork.test
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import millfork.Cpu
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import millfork.test.emu.{EmuUnoptimizedCrossPlatformRun, EmuUnoptimizedIntel8080Run, EmuUnoptimizedIntel8085Run, EmuUnoptimizedR800Run, EmuUnoptimizedSharpRun, EmuUnoptimizedZ80NextRun, EmuUnoptimizedZ80Run}
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import org.scalatest.{FunSuite, Matchers}
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/**
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* @author Karol Stasiak
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*/
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class Z80AssemblySuite extends FunSuite with Matchers {
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test("Common I80 instructions (Zilog syntax)") {
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EmuUnoptimizedIntel8080Run(
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"""
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| #pragma zilog_syntax
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| asm void main () {
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| ret
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| nop
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| ld bc,$101
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| ld (bc),a
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| inc bc
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| inc b
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| dec b
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| ld b,6
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| rlca
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| add hl,bc
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| ld a,(bc)
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| dec bc
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| inc c
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| dec c
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| ld c,$e
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| rrca
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| ld de,$1111
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| ld (de),a
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| inc de
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| inc d
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| dec d
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| ld d,$16
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| rla
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| add hl,de
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| ld a,(de)
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| dec de
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| inc e
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| dec e
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| ld e,$1e
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| rra
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| ld hl,$2121
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| inc hl
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| inc h
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| dec h
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| ld h,$26
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| daa
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| add hl,hl
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| dec hl
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| inc l
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| dec l
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| ld l,$2e
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| cpl
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| ld sp,$3131
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| ld ($fffe),a
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| inc sp
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| inc (hl)
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| dec (hl)
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| ld (hl),$36
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| scf
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| add hl,sp
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| ld a,($fffe)
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| dec sp
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| inc a
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| dec a
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| ld a,$3e
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| ccf
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| ld b,b
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| ld b,c
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| ld b,d
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| ld b,e
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| ld b,h
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| ld b,l
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| ld b,(hl)
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| ld b,a
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| ld c,b
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| ld c,c
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| ld c,d
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| ld c,e
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| ld c,h
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| ld c,l
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| ld c,(hl)
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| ld c,a
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| ld d,b
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| ld d,c
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| ld d,d
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| ld d,e
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| ld d,h
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| ld d,l
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| ld d,(hl)
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| ld d,a
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| ld e,b
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| ld e,c
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| ld e,d
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| ld e,e
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| ld e,h
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| ld e,l
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| ld e,(hl)
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| ld e,a
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| ld h,b
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| ld h,c
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| ld h,d
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| ld h,e
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| ld h,h
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| ld h,l
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| ld h,(hl)
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| ld h,a
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| ld l,b
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| ld l,c
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| ld l,d
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| ld l,e
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| ld l,h
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| ld l,l
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| ld l,(hl)
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| ld l,a
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| ld (hl),b
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| ld (hl),c
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| ld (hl),d
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| ld (hl),e
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| ld (hl),h
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| ld (hl),l
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| halt
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| ld (hl),a
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| ld a,b
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| ld a,c
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| ld a,d
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| ld a,e
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| ld a,h
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| ld a,l
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| ld a,(hl)
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| ld a,a
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| add a,b
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| add a,c
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| add a,d
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| add a,e
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| add a,h
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| add a,l
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| add a,(hl)
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| add a,a
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| adc a,b
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| adc a,c
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| adc a,d
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| adc a,e
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| adc a,h
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| adc a,l
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| adc a,(hl)
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| adc a,a
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| sub b
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| sub c
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| sub d
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| sub e
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| sub h
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| sub l
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| sub (hl)
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| sub a
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| sbc a,b
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| sbc a,c
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| sbc a,d
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| sbc a,e
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| sbc a,h
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| sbc a,l
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| sbc a,(hl)
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| sbc a,a
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| and b
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| and c
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| and d
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| and e
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| and h
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| and l
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| and (hl)
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| and a
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| xor b
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| xor c
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| xor d
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| xor e
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| xor h
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| xor l
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| xor (hl)
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| xor a
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| or b
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| or c
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| or d
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| or e
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| or h
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| or l
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| or (hl)
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| or a
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| cp b
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| cp c
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| cp d
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| cp e
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| cp h
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| cp l
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| cp (hl)
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| cp a
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| ret nz
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| pop bc
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| jp nz,main
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| jp main
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| call nz,main
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| push bc
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| add a,1
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| rst 0
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| ret z
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| ret
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| jp z,main
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| call z,main
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| call main
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| adc a,1
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| rst 8
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| ret nc
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| pop de
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| jp nc,main
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| call nc,main
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| push de
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| sub 1
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| rst $10
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| ret c
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| jp c,main
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| call c,main
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| sbc a,1
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| rst $18
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| pop hl
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| ex (sp),hl
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| push hl
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| and 1
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| rst $20
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| jp (hl)
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| xor 1
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| rst $28
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| pop af
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| di
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| push af
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| or 1
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| rst $30
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| ld sp,hl
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| ei
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| cp 1
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| rst $38
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| ret
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| }
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""".stripMargin)
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}
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test("Intel hex syntax disambiguation") {
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EmuUnoptimizedCrossPlatformRun(Cpu.Intel8080)(
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"""
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| #pragma intel_syntax
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| asm void main () {
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| lxi h, 0c000h
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| mvi m, 0b1h
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| mvi m, 0b1_h
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| mvi m, 0b_1_h
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| inx h
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| mvi m, 0b1
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| mvi m, 0b_1
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| ret
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| }
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| """.stripMargin){m =>
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m.readByte(0xc000) should equal(0xb1)
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m.readByte(0xc001) should equal(1)
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}
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}
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test("Common I80 instructions (without RST, Intel syntax)") {
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EmuUnoptimizedCrossPlatformRun(Cpu.Intel8080, Cpu.Intel8086)(
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"""
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| #pragma intel_syntax
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| asm void main () {
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| ret
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| nop
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| lxi b, 0101h
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| stax b
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| inx b
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| inr b
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| dcr b
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| mvi b,6h
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| rlc
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| dad b
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| ldax b
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| dcx b
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| inr c
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| dcr c
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| mvi c,0e_h
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| rrc
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| lxi d,11_11h
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| stax d
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| inx d
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| inr d
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| dcr d
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| mvi d,16h
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| ral
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| dad d
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| ldax d
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| dcx d
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| inr d
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| dcr d
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| mvi e, 1eh
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| rar
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| lxi h, 2121h
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| inx h
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| inr h
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| dcr h
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| mvi h,26h
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| daa
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| dad h
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| dcx h
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| inr l
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| dcr l
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| mvi l,2eh
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| cma
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| lxi sp, 3131h
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| sta 0fffeh
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| inx sp
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| inr m
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| dcr m
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| mvi m, 36h
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| stc
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| dad sp
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| lda 0fffeh
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| dcx sp
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| inr a
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| dcr a
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| mvi a, 3eh
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| cmc
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| mov b,b
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| mov b,c
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| mov b,d
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| mov b,e
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| mov b,h
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| mov b,l
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| mov b,m
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| mov b,a
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| mov c,b
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| mov c,c
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| mov c,d
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| mov c,e
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| mov c,h
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| mov c,l
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| mov c,m
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| mov c,a
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| mov d,b
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| mov d,c
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| mov d,d
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| mov d,e
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| mov d,h
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| mov d,l
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| mov d,m
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| mov d,a
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|
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| mov e,b
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| mov e,c
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| mov e,d
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| mov e,e
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| mov e,h
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| mov e,l
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| mov e,m
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| mov e,a
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|
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| mov h,b
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| mov h,c
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| mov h,d
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| mov h,e
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| mov h,h
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| mov h,l
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| mov h,m
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| mov h,a
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|
|
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| mov l,b
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| mov l,c
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| mov l,d
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| mov l,e
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| mov l,h
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| mov l,l
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| mov l,m
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| mov l,a
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| mov m,b
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| mov m,c
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| mov m,d
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| mov m,e
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| mov m,h
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| mov m,l
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| hlt
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| mov m,a
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| mov a,b
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| mov a,c
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| mov a,d
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| mov a,e
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| mov a,h
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| mov a,l
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| mov a,m
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| mov a,a
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|
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| add b
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| add c
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| add d
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| add e
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| add h
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| add l
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| add m
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| add a
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| adc b
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| adc c
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| adc d
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| adc e
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| adc h
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| adc l
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| adc m
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| adc a
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| sub b
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| sub c
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| sub d
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| sub e
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| sub h
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| sub l
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| sub m
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| sub a
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| sbb b
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| sbb c
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| sbb d
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| sbb e
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| sbb h
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| sbb l
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| sbb m
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| sbb a
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| ana b
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| ana c
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| ana d
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| ana e
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| ana h
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| ana l
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| ana m
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| ana a
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| xra b
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| xra c
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| xra d
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| xra e
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| xra h
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| xra l
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| xra m
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| xra a
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| ora b
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| ora c
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| ora d
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| ora e
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| ora h
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| ora l
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| ora m
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| ora a
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| cmp b
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| cmp c
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| cmp d
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| cmp e
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| cmp h
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| cmp l
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| cmp m
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| cmp a
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| rnz
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| pop b
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| jnz main
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| jmp main
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| cnz main
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| push b
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| adi 1_h
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| rz
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| ret
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| jz main
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| cz main
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| call main
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| aci 1
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| rnc
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| pop d
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| jnc main
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| cnc main
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| push d
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| sui 1
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| rc
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| jc main
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| cc main
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| sbi 1
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| pop h
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| xthl
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| push h
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| ani 1
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| pchl
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| xri 1
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| pop psw
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| di
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| push psw
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| ori 1
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| sphl
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| ei
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| cpi 1
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| ret
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| }
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""".stripMargin){ m => }
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}
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|
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test("Intel 8080 instructions (Zilog syntax)") {
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EmuUnoptimizedIntel8080Run(
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"""
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| #pragma zilog_syntax
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| asm void main () {
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| ret
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| ld ($fffe),hl
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| ld hl,($fffe)
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| out (1),a
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| in a,(1)
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| ret po
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| jp po,main
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| call po,main
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| ret pe
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| jp pe,main
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| ex de,hl
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| call pe,main
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| ret p
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| jp p,main
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| call p,main
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| ret m
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| jp m,main
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| call m,main
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|
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| ret
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| }
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""".stripMargin)
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}
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|
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test("Intel 8080 instructions (Intel syntax)") {
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EmuUnoptimizedCrossPlatformRun(Cpu.Intel8080, Cpu.Intel8086)(
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"""
|
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| #pragma intel_syntax
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| asm void main () {
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| ret
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| shld 0fffeh
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| lhld 0fffeh
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| out 1
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| in 1
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| rpo
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| jpo main
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| cpo main
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| rpe
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| jpe main
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| xchg
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| cpe main
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| rp
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| jp main
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| cp main
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| rm
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| jm main
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| cm main
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| ret
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| }
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""".stripMargin){ m => }
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}
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|
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test("Intel 8080 RST instructions (Intel syntax)") {
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EmuUnoptimizedIntel8080Run(
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"""
|
|
| #pragma intel_syntax
|
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| asm void main () {
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| ret
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| rst 0
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| rst 1
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| rst 2
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| rst 3
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| rst 4
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| rst 5
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| rst 6
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| rst 7
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|
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| ret
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| }
|
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""".stripMargin)
|
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}
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|
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test("Extended I80 instructions") {
|
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EmuUnoptimizedZ80Run(
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"""
|
|
| asm void main () {
|
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| ret
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|
|
|
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| reti
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|
|
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| jr main
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| jr nz,main
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| jr z,main
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| jr nc,main
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| jr c,main
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| ld (34),sp
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| rlc b
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| rlc c
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| rlc d
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| rlc e
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| rlc h
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| rlc l
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| rlc (hl)
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| rlc a
|
|
|
|
|
| rrc b
|
|
| rrc c
|
|
| rrc d
|
|
| rrc e
|
|
| rrc h
|
|
| rrc l
|
|
| rrc (hl)
|
|
| rrc a
|
|
|
|
|
| rl b
|
|
| rl c
|
|
| rl d
|
|
| rl e
|
|
| rl h
|
|
| rl l
|
|
| rl (hl)
|
|
| rl a
|
|
|
|
|
| rr b
|
|
| rr c
|
|
| rr d
|
|
| rr e
|
|
| rr h
|
|
| rr l
|
|
| rr (hl)
|
|
| rr a
|
|
|
|
|
| sla b
|
|
| sla c
|
|
| sla d
|
|
| sla e
|
|
| sla h
|
|
| sla l
|
|
| sla (hl)
|
|
| sla a
|
|
|
|
|
| sra b
|
|
| sra c
|
|
| sra d
|
|
| sra e
|
|
| sra h
|
|
| sra l
|
|
| sra (hl)
|
|
| sra a
|
|
|
|
|
| srl b
|
|
| srl c
|
|
| srl d
|
|
| srl e
|
|
| srl h
|
|
| srl l
|
|
| srl (hl)
|
|
| srl a
|
|
|
|
|
| bit 1,a
|
|
| res 1,a
|
|
| set 1,a
|
|
| bit 1,(hl)
|
|
| res 1,(hl)
|
|
| set 1,(hl)
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 instructions with IX") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| asm void main () {
|
|
| ret
|
|
| add a,ix(1)
|
|
| adc a,ix(2)
|
|
| sub ix(3)
|
|
| sbc a,ix(0)
|
|
| and ix(0)
|
|
| xor ix(0)
|
|
| or ix(0)
|
|
| cp ix(0)
|
|
|
|
|
| rrc ix(0)
|
|
| rr ix(0)
|
|
| rlc ix(0)
|
|
| rl ix(0)
|
|
| sla ix(0)
|
|
| sra ix(0)
|
|
| srl ix(0)
|
|
| sll ix(0)
|
|
|
|
|
| pop ix
|
|
| push ix
|
|
| add ix,sp
|
|
| add ix,ix
|
|
| add ix,de
|
|
| add ix,bc
|
|
| inc ix
|
|
| dec ix
|
|
| ld ix,3
|
|
| ld ix,(3)
|
|
| ld (3),ix
|
|
| ex (sp),ix
|
|
| jp (ix)
|
|
| ld sp,ix
|
|
| ld a,ix(2)
|
|
| ld ix(2),a
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 instructions with IY") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| asm void main () {
|
|
| ret
|
|
| add a,iy(1)
|
|
| adc a,iy(2)
|
|
| sub iy(3)
|
|
| sbc a,iy(0)
|
|
| and iy(0)
|
|
| xor iy(0)
|
|
| or iy(0)
|
|
| cp iy(0)
|
|
|
|
|
| rrc iy(0)
|
|
| rr iy(0)
|
|
| rlc iy(0)
|
|
| rl iy(0)
|
|
| sla iy(0)
|
|
| sra iy(0)
|
|
| srl iy(0)
|
|
| sll iy(0)
|
|
|
|
|
| pop iy
|
|
| push iy
|
|
| add iy,sp
|
|
| add iy,iy
|
|
| add iy,de
|
|
| add iy,bc
|
|
| inc iy
|
|
| dec iy
|
|
| ld iy,3
|
|
| ld iy,(3)
|
|
| ld (3),iy
|
|
| ex (sp),iy
|
|
| jp (iy)
|
|
| ld sp,iy
|
|
| ld a,iy(2)
|
|
| ld iy(2),a
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Other Z80 instructions") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| asm void main () {
|
|
| ret
|
|
|
|
|
| djnz main
|
|
| ex af,af'
|
|
| exx
|
|
|
|
|
| sll b
|
|
| sll c
|
|
| sll d
|
|
| sll e
|
|
| sll h
|
|
| sll l
|
|
| sll (hl)
|
|
| sll a
|
|
|
|
|
| in b,(c)
|
|
| out(c),b
|
|
| sbc hl,bc
|
|
| ld (34),bc
|
|
| neg
|
|
| retn
|
|
| im 0
|
|
| ld i,a
|
|
| in c,(c)
|
|
| out (c),c
|
|
| adc hl,bc
|
|
| ld bc,(7)
|
|
| ld r,a
|
|
| in d,(c)
|
|
| out (c),d
|
|
| sbc hl,de
|
|
| ld (55),de
|
|
| im 1
|
|
| ld a,i
|
|
| in e,(c)
|
|
| out (c),e
|
|
| adc hl,de
|
|
| ld de,(33)
|
|
| im 2
|
|
| ld a,r
|
|
|
|
|
| in h,(c)
|
|
| out (c),h
|
|
| sbc hl,hl
|
|
| rrd
|
|
| in l,(c)
|
|
| out (c),l
|
|
| adc hl,hl
|
|
| rld
|
|
| sbc hl,sp
|
|
| in a,(c)
|
|
| out (c),a
|
|
| adc hl,sp
|
|
| ld sp,(345)
|
|
|
|
|
| ldi
|
|
| cpi
|
|
| ini
|
|
| outi
|
|
| ldd
|
|
| cpd
|
|
| ind
|
|
| outd
|
|
| ldir
|
|
| cpir
|
|
| inir
|
|
| otir
|
|
| lddr
|
|
| cpdr
|
|
| indr
|
|
| otdr
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Extended I80 instructions (Intel syntax)") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
|
|
|
| reti
|
|
|
|
|
| jmpr main
|
|
| jrnz main
|
|
| jrz main
|
|
| jrnc main
|
|
| jrc main
|
|
| lspd 34
|
|
|
|
|
| rlcr b
|
|
| rlcr c
|
|
| rlcr d
|
|
| rlcr e
|
|
| rlcr h
|
|
| rlcr l
|
|
| rlcr m
|
|
| rlcr a
|
|
|
|
|
| rrcr b
|
|
| rrcr c
|
|
| rrcr d
|
|
| rrcr e
|
|
| rrcr h
|
|
| rrcr l
|
|
| rrcr m
|
|
| rrcr a
|
|
|
|
|
| ralr b
|
|
| ralr c
|
|
| ralr d
|
|
| ralr e
|
|
| ralr h
|
|
| ralr l
|
|
| ralr m
|
|
| ralr a
|
|
|
|
|
| rarr b
|
|
| rarr c
|
|
| rarr d
|
|
| rarr e
|
|
| rarr h
|
|
| rarr l
|
|
| rarr m
|
|
| rarr a
|
|
|
|
|
| slar b
|
|
| slar c
|
|
| slar d
|
|
| slar e
|
|
| slar h
|
|
| slar l
|
|
| slar m
|
|
| slar a
|
|
|
|
|
| srar b
|
|
| srar c
|
|
| srar d
|
|
| srar e
|
|
| srar h
|
|
| srar l
|
|
| srar m
|
|
| srar a
|
|
|
|
|
| srlr b
|
|
| srlr c
|
|
| srlr d
|
|
| srlr e
|
|
| srlr h
|
|
| srlr l
|
|
| srlr m
|
|
| srlr a
|
|
|
|
|
| bit 1,a
|
|
| res 1,a
|
|
| setb 1,a
|
|
| set 1,a
|
|
| bit 1,m
|
|
| res 1,m
|
|
| setb 1,m
|
|
| set 1,m
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 instructions with IX (Intel syntax)") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| addx 0
|
|
| adcx 0
|
|
| subx 0
|
|
| sbcx 0
|
|
| andx 0
|
|
| xorx 0
|
|
| orx 0
|
|
| cmpx 0
|
|
|
|
|
| rrcx 0
|
|
| rarx 0
|
|
| rlcx 0
|
|
| ralx 0
|
|
| slax 0
|
|
| srax 0
|
|
| srlx 0
|
|
| sllx 0
|
|
|
|
|
| popix
|
|
| pushix
|
|
| pop ix
|
|
| push ix
|
|
| dadx sp
|
|
| dadx ix
|
|
| dadx d
|
|
| dadx b
|
|
| inxix
|
|
| dcxix
|
|
| inx ix
|
|
| dcx ix
|
|
| lxix 3
|
|
| lixd 3
|
|
| sixd 3
|
|
| xtix
|
|
| pcix
|
|
| spix
|
|
| ldx a,0
|
|
| stx a,0
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 instructions with IY (Intel syntax)") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| addy 0
|
|
| adcy 0
|
|
| suby 0
|
|
| sbcy 0
|
|
| andy 0
|
|
| xory 0
|
|
| ory 0
|
|
| cmpy 0
|
|
|
|
|
| rrcy 0
|
|
| rary 0
|
|
| rlcy 0
|
|
| raly 0
|
|
| slay 0
|
|
| sray 0
|
|
| srly 0
|
|
| slly 0
|
|
|
|
|
| popiy
|
|
| pushiy
|
|
| pop iy
|
|
| push iy
|
|
| dady sp
|
|
| dady iy
|
|
| dady d
|
|
| dady b
|
|
| inxiy
|
|
| dcxiy
|
|
| inx iy
|
|
| dcx iy
|
|
| lxiy 3
|
|
| liyd 3
|
|
| siyd 3
|
|
| xtiy
|
|
| pciy
|
|
| spiy
|
|
| ldy a,0
|
|
| sty a,0
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Other Z80 instructions (Intel syntax)") {
|
|
EmuUnoptimizedZ80Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
|
|
|
| djnz main
|
|
| exaf
|
|
| exx
|
|
|
|
|
| sllr b
|
|
| sllr c
|
|
| sllr d
|
|
| sllr e
|
|
| sllr h
|
|
| sllr l
|
|
| sllr m
|
|
| sllr a
|
|
|
|
|
| inp b
|
|
| outp b
|
|
| dsbc b
|
|
| lbcd 34
|
|
| neg
|
|
| retn
|
|
| im0
|
|
| stai
|
|
| inp c
|
|
| outp c
|
|
| dadc b
|
|
| lbcd 7
|
|
| star
|
|
| inp d
|
|
| outp d
|
|
| dsbc d
|
|
| lded 55
|
|
| im1
|
|
| ldai
|
|
| inp e
|
|
| outp e
|
|
| dadc d
|
|
| lded 33
|
|
| im2
|
|
| ldar
|
|
|
|
|
| inp h
|
|
| outp h
|
|
| dsbc h
|
|
| rrd
|
|
| inp l
|
|
| outp l
|
|
| dadc h
|
|
| rld
|
|
| dsbc sp
|
|
| inp a
|
|
| outp a
|
|
| dadc sp
|
|
| lspd 345
|
|
|
|
|
| ldi
|
|
| cci
|
|
| ini
|
|
| outi
|
|
| ldd
|
|
| ccd
|
|
| ind
|
|
| outd
|
|
| ldir
|
|
| ccir
|
|
| inir
|
|
| outir
|
|
| lddr
|
|
| ccdr
|
|
| indr
|
|
| outdr
|
|
|
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Gameboy instructions") {
|
|
EmuUnoptimizedSharpRun(
|
|
"""
|
|
| asm void main () {
|
|
| ret
|
|
| ld (8),sp
|
|
| stop
|
|
| ld (hli),a
|
|
| ld (hld),a
|
|
| ld a,(hli)
|
|
| ld a,(hld)
|
|
| reti
|
|
| add sp,3
|
|
| ld hl,sp+3
|
|
| swap a
|
|
| swap b
|
|
| swap c
|
|
| swap(hl)
|
|
|
|
|
| ldh a,(9)
|
|
| ldh (9),a
|
|
| ldh a,(c)
|
|
| ldh (c),a
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
|
|
test("Intel 8085 instructions (Zilog syntax)") {
|
|
EmuUnoptimizedIntel8085Run(
|
|
"""
|
|
| #pragma zilog_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| rim
|
|
| sim
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
|
|
test("Intel 8085 instructions (Intel syntax)") {
|
|
EmuUnoptimizedIntel8085Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| rim
|
|
| sim
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Illegal Intel 8085 instructions (Intel syntax)") {
|
|
EmuUnoptimizedIntel8085Run(
|
|
"""
|
|
| #pragma intel_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| lhlx
|
|
| shlx
|
|
| arhl
|
|
| rlde
|
|
| ldhi 5
|
|
| ldsi 6
|
|
| rstv
|
|
| ovrst8
|
|
| jk main
|
|
| jnk main
|
|
| jx5 main
|
|
| jnx5 main
|
|
| dsub
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Illegal Intel 8085 instructions (Zilog syntax)") {
|
|
EmuUnoptimizedIntel8085Run(
|
|
"""
|
|
| #pragma zilog_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| ld hl,(de)
|
|
| ld (de), hl
|
|
| sra hl
|
|
| rl de
|
|
| ld de,hl+5
|
|
| ld de,sp+6
|
|
| rstv
|
|
| jp k, main
|
|
| jp nk, main
|
|
| jp x5, main
|
|
| jp nx5, main
|
|
| dsub
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 Next instructions (Zilog syntax)") {
|
|
EmuUnoptimizedZ80NextRun(
|
|
"""
|
|
| #pragma zilog_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| ldix
|
|
| ldws
|
|
| ldirx
|
|
| lddx
|
|
| lddrx
|
|
| ldpirx
|
|
| outinb
|
|
| mul
|
|
| mul d,e
|
|
| add hl,a
|
|
| add de,a
|
|
| add bc,a
|
|
| add hl,1
|
|
| add de,2
|
|
| add bc,3
|
|
| swapnib
|
|
| mirror
|
|
| mirror a
|
|
| push $5555
|
|
| nextreg 1,2
|
|
| nextreg 1,a
|
|
| pixeldn
|
|
| pixelad
|
|
| setae
|
|
| test 8
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("Z80 halves of index registers") {
|
|
EmuUnoptimizedZ80NextRun(
|
|
"""
|
|
| #pragma zilog_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| inc ixh
|
|
| inc ixl
|
|
| inc iyh
|
|
| inc iyl
|
|
| dec ixh
|
|
| dec ixl
|
|
| dec iyh
|
|
| dec iyl
|
|
| ld a,ixh
|
|
| ld a,ixl
|
|
| ld iyh,a
|
|
| ld iyl,a
|
|
| add a,iyl
|
|
| adc a,iyl
|
|
| sub iyl
|
|
| sbc a,iyl
|
|
| or iyl
|
|
| xor iyl
|
|
| and iyl
|
|
| cp iyl
|
|
| ld ixh,0
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
test("R800 stuff") {
|
|
EmuUnoptimizedR800Run(
|
|
"""
|
|
| #pragma zilog_syntax
|
|
| asm void main () {
|
|
| ret
|
|
| mulub a,b
|
|
| mulub a,c
|
|
| mulub a,d
|
|
| mulub a,e
|
|
| muluw hl,bc
|
|
| muluw hl,sp
|
|
| inc ixh
|
|
| inc ixl
|
|
| inc iyh
|
|
| inc iyl
|
|
| dec ixh
|
|
| dec ixl
|
|
| dec iyh
|
|
| dec iyl
|
|
| ld a,ixh
|
|
| ld a,ixl
|
|
| ld iyh,a
|
|
| ld iyl,a
|
|
| add a,iyl
|
|
| adc a,iyl
|
|
| sub iyl
|
|
| sbc a,iyl
|
|
| or iyl
|
|
| xor iyl
|
|
| and iyl
|
|
| cp iyl
|
|
| ld ixh,0
|
|
| ret
|
|
| }
|
|
""".stripMargin)
|
|
}
|
|
|
|
}
|