mirror of
https://github.com/KarolS/millfork.git
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244 lines
13 KiB
Scala
244 lines
13 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.assembly.mos.{AddrMode, AssemblyLine, AssemblyLine0, OpcodeClasses}
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import millfork.assembly.{AssemblyOptimization, Elidability, OptimizationContext}
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import millfork.env.NormalFunction
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import millfork.error.Logger
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import scala.annotation.tailrec
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import scala.util.control.TailCalls.{TailRec, done, tailcall}
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/**
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* @author Karol Stasiak
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*/
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object ChangeIndexRegisterOptimizationPreferringX2Y extends ChangeIndexRegisterOptimization(true)
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object ChangeIndexRegisterOptimizationPreferringY2X extends ChangeIndexRegisterOptimization(false)
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class ChangeIndexRegisterOptimization(preferX2Y: Boolean) extends AssemblyOptimization[AssemblyLine] {
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object IndexReg extends Enumeration {
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val X, Y = Value
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}
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object IndexDirection extends Enumeration {
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val X2Y, Y2X = Value
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}
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import IndexReg._
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import IndexDirection._
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import millfork.assembly.mos.AddrMode._
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import millfork.assembly.mos.Opcode._
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type IndexReg = IndexReg.Value
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type IndexDirection = IndexDirection.Value
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override def name = "Changing index registers"
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override def optimize(f: NormalFunction, code: List[AssemblyLine], optimizationContext: OptimizationContext): List[AssemblyLine] = {
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val addressingModesUsingX = Set(AbsoluteX, ZeroPageX, IndexedX)
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val addressingModesUsingY = Set(AbsoluteY, ZeroPageY, IndexedY, LongIndexedY, IndexedSY)
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val usesX = code.exists(l =>
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OpcodeClasses.ReadsXAlways(l.opcode) ||
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OpcodeClasses.ChangesX(l.opcode) ||
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addressingModesUsingX(l.addrMode)
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)
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val usesY = code.exists(l => {
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OpcodeClasses.ReadsYAlways(l.opcode) ||
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OpcodeClasses.ChangesY(l.opcode) ||
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addressingModesUsingY(l.addrMode)
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}
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)
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if (!usesX && !usesY) {
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return code
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}
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val canX2Y = f.returnType.size <= 1 && canOptimize(code, X2Y, None)
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val canY2X = canOptimize(code, Y2X, None)
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implicit val log: Logger = optimizationContext.log
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(canX2Y, canY2X) match {
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case (false, false) => code
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case (true, false) =>
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if (!usesX) code else {
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log.debug("Changing index register from X to Y")
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val changed = switchX2Y(code).result
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traceDiff(code, changed)
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changed
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}
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case (false, true) =>
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if (!usesY) code else {
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log.debug("Changing index register from Y to X")
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val changed = switchY2X(code).result
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traceDiff(code, changed)
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changed
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}
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case (true, true) =>
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if (preferX2Y) {
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if (!usesX) code else {
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log.debug("Changing index register from X to Y (arbitrarily)")
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val changed = switchX2Y(code).result
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traceDiff(code, changed)
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changed
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}
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} else {
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if (!usesY) code else {
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log.debug("Changing index register from Y to X (arbitrarily)")
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val changed = switchY2X(code).result
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traceDiff(code, changed)
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changed
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}
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}
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}
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}
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private def traceDiff(original: List[AssemblyLine], changed: List[AssemblyLine])(implicit log: Logger): Unit = {
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if (log.traceEnabled) {
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original.zip(changed).foreach{
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case (o, n) =>
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if (o.addrMode == n.addrMode && o.opcode == n.opcode) log.trace(n.toString)
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else log.trace(f"$o%-30s → $n%s")
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}
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}
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}
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//noinspection OptionEqualsSome
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@tailrec
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private def canOptimize(code: List[AssemblyLine], dir: IndexDirection, loaded: Option[IndexReg]): Boolean = {
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val notX = loaded != Some(X)
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val notY = loaded != Some(Y)
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code match {
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case AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | STZ | LDZ | BIT, AbsoluteX | ZeroPageX, _) :: xs if dir == X2Y => false
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case AssemblyLine0(LDY | STY, AbsoluteX | ZeroPageX, _) :: xs => false
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case AssemblyLine0(LDX | STX, AbsoluteY | ZeroPageY, _) :: xs => false
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case AssemblyLine0(_, AbsoluteY, _) :: xs if notY => false
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case AssemblyLine0(_, ZeroPageY, _) :: xs if notY => false
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case AssemblyLine0(_, IndexedY, _) :: xs if dir == Y2X || notY => false
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case AssemblyLine0(_, LongIndexedY, _) :: xs if dir == Y2X || notY => false
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case AssemblyLine0(_, IndexedSY, _) :: xs if dir == Y2X || notY => false
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case AssemblyLine0(_, AbsoluteX, _) :: xs if notX => false
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case AssemblyLine0(_, LongAbsoluteX, _) :: xs if notX => false
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case AssemblyLine0(_, ZeroPageX, _) :: xs if notX => false
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case AssemblyLine0(_, IndexedX | ImmediateWithAbsoluteX | ImmediateWithZeroPageX, _) :: xs if dir == X2Y || notX => false
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case AssemblyLine0(_, AbsoluteIndexedX, _) :: xs if dir == X2Y => false
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case AssemblyLine0(SHX | SHY | AHX | TAS | LAS, _, _) :: xs => false
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case AssemblyLine(TXY, _, _, e, _) :: xs => (e == Elidability.Elidable || e == Elidability.Volatile) && loaded == Some(X) && canOptimize(xs, dir, Some(Y))
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case AssemblyLine(TYX, _, _, e, _) :: xs => (e == Elidability.Elidable || e == Elidability.Volatile) && loaded == Some(Y) && canOptimize(xs, dir, Some(X))
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// using a wrong index register for one instruction is fine
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case AssemblyLine0(LDY | TAY, _, _) :: AssemblyLine0(_, IndexedY, _) :: xs if dir == Y2X =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LDX | TAX, _, _) :: AssemblyLine0(_, IndexedX, _) :: xs if dir == X2Y =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LDX | TAX, _, _) :: AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | STZ, AbsoluteX | ZeroPageX, _) :: xs if dir == X2Y =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LDY | TAY, _, _) :: AssemblyLine0(INY | DEY, _, _) :: AssemblyLine0(_, IndexedY, _) :: xs if dir == Y2X =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LDX | TAX, _, _) :: AssemblyLine0(INX | DEX, _, _) :: AssemblyLine0(_, IndexedX, _) :: xs if dir == X2Y =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LDX | TAX, _, _) :: AssemblyLine0(INX | DEX, _, _) :: AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | STZ, AbsoluteX | ZeroPageX, _) :: xs if dir == X2Y =>
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canOptimize(xs, dir, None)
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case AssemblyLine0(LAX, _, _) :: xs => false
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case AssemblyLine0(JSR | BSR, _, _) :: xs => false // TODO
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case AssemblyLine0(JMP, Absolute, _) :: xs => canOptimize(xs, dir, None) // TODO
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case AssemblyLine0(op, _, _) :: xs if OpcodeClasses.ShortBranching(op) => canOptimize(xs, dir, None)
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case AssemblyLine0(RTS | RTL | BRA | BRL, _, _) :: xs => canOptimize(xs, dir, None)
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case AssemblyLine0(LABEL, _, _) :: xs => canOptimize(xs, dir, None)
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case AssemblyLine0(DISCARD_XF, _, _) :: xs => canOptimize(xs, dir, loaded.filter(_ != X))
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case AssemblyLine0(DISCARD_YF, _, _) :: xs => canOptimize(xs, dir, loaded.filter(_ != Y))
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case AssemblyLine0(_, DoesNotExist, _) :: xs => canOptimize(xs, dir, loaded)
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case AssemblyLine(TAX | LDX | PLX, _, _, e, _) :: xs =>
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(e == Elidability.Elidable || e == Elidability.Volatile || dir == Y2X) && canOptimize(xs, dir, Some(X))
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case AssemblyLine(TAY | LDY | PLY, _, _, e, _) :: xs =>
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(e == Elidability.Elidable || e == Elidability.Volatile || dir == X2Y) && canOptimize(xs, dir, Some(Y))
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case AssemblyLine(TXA | STX | PHX | CPX | INX | DEX | HuSAX, _, _, e, _) :: xs =>
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(e == Elidability.Elidable || e == Elidability.Volatile || dir == Y2X) && loaded == Some(X) && canOptimize(xs, dir, Some(X))
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case AssemblyLine(TYA | STY | PHY | CPY | INY | DEY | SAY, _, _, e, _) :: xs =>
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(e == Elidability.Elidable || e == Elidability.Volatile || dir == X2Y) && loaded == Some(Y) && canOptimize(xs, dir, Some(Y))
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case AssemblyLine0(SAX | TXS | SBX, _, _) :: xs => dir == Y2X && loaded == Some(X) && canOptimize(xs, dir, Some(X))
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case AssemblyLine0(TSX, _, _) :: xs => dir == Y2X && notY && canOptimize(xs, dir, Some(X))
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case _ :: xs => canOptimize(xs, dir, loaded)
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case Nil => true
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}
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}
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private def switchX2Y(code: List[AssemblyLine])(implicit log: Logger): TailRec[List[AssemblyLine]] = code match {
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (b@AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | LDY | STY | STZ, AbsoluteX | ZeroPageX, _))
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:: xs => tailcall(switchX2Y(xs)).map(a :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (b@AssemblyLine0(_, IndexedX, _))
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:: xs => tailcall(switchX2Y(xs)).map(a :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (i@AssemblyLine0(INX | DEX, _, _))
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:: (b@AssemblyLine0(INC | DEC | ASL | ROL | ROR | LSR | LDY | STY | STZ, AbsoluteX | ZeroPageX, _))
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:: xs => tailcall(switchX2Y(xs)).map(a :: i :: b :: _)
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case (a@AssemblyLine0(LDX | TAX, _, _))
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:: (i@AssemblyLine0(INX | DEX, _, _))
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:: (b@AssemblyLine0(_, IndexedX, _))
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:: xs => tailcall(switchX2Y(xs)).map(a :: i :: b :: _)
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case (x@AssemblyLine0(TAX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TAY) :: _)
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case (x@AssemblyLine0(TXA, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TYA) :: _)
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case (x@AssemblyLine0(TXY | TYX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = TYX) :: _) // keep the transfer for the flags
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case (x@AssemblyLine0(STX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = STY) :: _)
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case (x@AssemblyLine0(LDX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = LDY) :: _)
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case (x@AssemblyLine0(INX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = INY) :: _)
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case (x@AssemblyLine0(DEX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = DEY) :: _)
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case (x@AssemblyLine0(CPX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = CPY) :: _)
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case (x@AssemblyLine0(PHX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = PHY) :: _)
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case (x@AssemblyLine0(PLX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = PLY) :: _)
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case (x@AssemblyLine0(HuSAX, _, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(opcode = SAY) :: _)
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case AssemblyLine0(LAX, _, _) :: xs => log.fatal("Unexpected LAX")
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case AssemblyLine0(TXS, _, _) :: xs => log.fatal("Unexpected TXS")
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case AssemblyLine0(TSX, _, _) :: xs => log.fatal("Unexpected TSX")
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case AssemblyLine0(SBX, _, _) :: xs => log.fatal("Unexpected SBX")
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case AssemblyLine0(SAX, _, _) :: xs => log.fatal("Unexpected SAX")
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case AssemblyLine0(SXY, _, _) :: xs => log.fatal("Unexpected SXY")
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case (x@AssemblyLine0(_, AbsoluteX, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(addrMode = AbsoluteY) :: _)
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case (x@AssemblyLine0(_, ZeroPageX, _)) :: xs => tailcall(switchX2Y(xs)).map(x.copy(addrMode = ZeroPageY) :: _)
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case (x@AssemblyLine0(_, IndexedX, _)) :: xs => log.fatal("Unexpected IndexedX")
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case x::xs => tailcall(switchX2Y(xs)).map(x :: _)
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case Nil => done(Nil)
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}
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private def switchY2X(code: List[AssemblyLine])(implicit log: Logger): TailRec[List[AssemblyLine]] = code match {
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case AssemblyLine0(LDY | TAY, _, _)
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:: AssemblyLine0(_, IndexedY, _)
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:: xs => tailcall(switchY2X(xs)).map(code.take(2) ++ _)
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case AssemblyLine0(LDY | TAY, _, _)
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:: (i@AssemblyLine0(INY | DEY, _, _))
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:: AssemblyLine0(_, IndexedY, _)
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:: xs => tailcall(switchY2X(xs)).map(code.take(3) ++ _)
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case (x@AssemblyLine0(TAY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TAX) :: _)
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case (x@AssemblyLine0(TYA, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TXA) :: _)
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case (x@AssemblyLine0(TYX | TXY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = TXY) :: _) // keep the transfer for the flags
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case (x@AssemblyLine0(STY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = STX) :: _)
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case (x@AssemblyLine0(LDY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = LDX) :: _)
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case (x@AssemblyLine0(INY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = INX) :: _)
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case (x@AssemblyLine0(DEY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = DEX) :: _)
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case (x@AssemblyLine0(CPY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = CPX) :: _)
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case (x@AssemblyLine0(PHY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = PHX) :: _)
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case (x@AssemblyLine0(PLY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = PLX) :: _)
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case (x@AssemblyLine0(SAY, _, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(opcode = HuSAX) :: _)
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case AssemblyLine0(SXY, _, _) :: xs => log.fatal("Unexpected SXY")
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case (x@AssemblyLine0(_, AbsoluteY, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(addrMode = AbsoluteX) :: _)
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case (x@AssemblyLine0(_, ZeroPageY, _)) :: xs => tailcall(switchY2X(xs)).map(x.copy(addrMode = ZeroPageX) :: _)
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case AssemblyLine0(_, IndexedY, _) :: xs => log.fatal("Unexpected IndexedY")
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case AssemblyLine0(_, LongIndexedY, _) :: xs => log.fatal("Unexpected LongIndexedY")
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case AssemblyLine0(_, IndexedSY, _) :: xs => log.fatal("Unexpected IndexedSY")
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case x::xs => tailcall(switchY2X(xs)).map(x :: _)
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case Nil => done(Nil)
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}
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}
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