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638 lines
37 KiB
Scala
638 lines
37 KiB
Scala
package millfork.assembly.mos.opt
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import millfork.assembly._
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import millfork.assembly.mos._
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import millfork.assembly.mos.Opcode._
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import AddrMode._
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import millfork.assembly.mos.OpcodeClasses._
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import millfork.env.{Constant, NormalFunction, NumericConstant}
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/**
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* These optimizations help on their own, but may prevent other optimizations from triggering.
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*
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* @author Karol Stasiak
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*/
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//noinspection ZeroIndexToHead
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object LaterOptimizations {
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private val LdxAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageY, AbsoluteY)
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private val LdyAddrModes = Set(Immediate, Absolute, ZeroPage, ZeroPageX, AbsoluteX)
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private val StxAddrModes = Set(Absolute, ZeroPage, ZeroPageY)
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private val StyAddrModes = Set(Absolute, ZeroPage, ZeroPageX)
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private val StaAddrModes = Set(Absolute, ZeroPage, ZeroPageX, AbsoluteX, IndexedY, IndexedX, AbsoluteY)
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private val CpxyAddrModes = Set(Immediate, Absolute, ZeroPage)
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// This optimization tends to prevent later Variable To Register Optimization,
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// so run this only after it's pretty sure V2RO won't happen any more
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val DoubleLoadToDifferentRegisters = new RuleBasedAssemblyOptimization("Double load to different registers",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA), LDX, TAX),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA), LDY, TAY),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX), LDA, TXA),
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TwoDifferentLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY), LDA, TYA),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA), LDX, TAX),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA), LDY, TAY),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX), LDA, TXA),
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TwoDifferentLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY), LDA, TYA),
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(HasOpcodeIn(Set(LDA, STA)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesA) & Not(HasOpcode(LDX)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAtAssumingNonchangingIndices(0, 1)).* ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~~> (code => code.init :+ AssemblyLine.implied(TAX)),
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(HasOpcodeIn(Set(LDA, STA)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesA) & Not(HasOpcode(LDY)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAtAssumingNonchangingIndices(0, 1)).* ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~~> (code => code.init :+ AssemblyLine.implied(TAY)),
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(HasOpcodeIn(Set(LDX, STX)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesX) & Not(HasOpcode(LDA)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAtAssumingNonchangingIndices(0, 1)).* ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~~> (code => code.init :+ AssemblyLine.implied(TXA)),
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(HasOpcodeIn(Set(LDY, STY)) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesY) & Not(HasOpcode(LDA)) & DoesntChangeIndexingInAddrMode(0) & DoesntChangeMemoryAtAssumingNonchangingIndices(0, 1)).* ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~~> (code => code.init :+ AssemblyLine.implied(TYA)),
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)
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private def a2x(line: AssemblyLine) = line.opcode match {
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case LDA => line.copy(opcode = LDX)
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case STA => line.copy(opcode = STX)
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case CMP => line.copy(opcode = CPX)
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case INC => line.copy(opcode = INX)
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case DEC => line.copy(opcode = DEX)
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}
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private def a2y(line: AssemblyLine) = line.opcode match {
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case LDA => line.copy(opcode = LDY)
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case STA => line.copy(opcode = STY)
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case CMP => line.copy(opcode = CPY)
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case INC => line.copy(opcode = INY)
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case DEC => line.copy(opcode = DEY)
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}
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private def x2a(line: AssemblyLine) = line.opcode match {
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case LDX => line.copy(opcode = LDA)
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case STX => line.copy(opcode = STA)
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case CPX => line.copy(opcode = CMP)
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case INX => line.copy(opcode = INC)
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case DEX => line.copy(opcode = DEC)
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}
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private def y2a(line: AssemblyLine) = line.opcode match {
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case LDY => line.copy(opcode = LDA)
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case STY => line.copy(opcode = STA)
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case CPY => line.copy(opcode = CMP)
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case INY => line.copy(opcode = INC)
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case DEY => line.copy(opcode = DEC)
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}
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val DoubleLoadToTwoRegistersWhenOneWillBeTrashed = new RuleBasedAssemblyOptimization("Double load to two registers when one will be trashed",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(NotFixed & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) ~
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(NotFixed & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsX)).+ ~
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(Elidable & (HasOpcode(TAX) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsX)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2x)),
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(NotFixed & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) ~
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(NotFixed & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesNotConcernMemoryAt(0, 1) & Not(ConcernsY)).+ ~
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(Elidable & (HasOpcode(TAY) | HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1) & Not(ConcernsY)) & DoesntMatterWhatItDoesWith(State.A)) ~~> (_.init.map(a2y)),
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(NotFixed & HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) ~
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(NotFixed & HasOpcode(STX) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
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(Elidable & (HasOpcode(TXA) | HasOpcode(LDX) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.X)) ~~> (_.init.map(x2a)),
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(NotFixed & HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) ~
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(NotFixed & HasOpcode(STY) & HasAddrModeIn(StaAddrModes) & DoesNotConcernMemoryAt(0, 1)).+ ~
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(Elidable & (HasOpcode(TYA) | HasOpcode(LDY) & MatchAddrMode(0) & MatchParameter(1)) & DoesntMatterWhatItDoesWith(State.Y)) ~~> (_.init.map(y2a)),
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)
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private def TwoDifferentLoadsWithNoFlagChangeInBetween(opcode1: Opcode.Value, middle: AssemblyLinePattern, opcode2: Opcode.Value, transferOpcode: Opcode.Value) = {
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(HasOpcode(opcode1) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesMemory) & DoesntChangeIndexingInAddrMode(0) & middle & Not(HasOpcode(opcode2))).* ~
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(HasOpcode(opcode2) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { c =>
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c.init :+ AssemblyLine.implied(transferOpcode)
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}
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}
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private def TwoDifferentLoadsWhoseFlagsWillNotBeChecked(opcode1: Opcode.Value, middle: AssemblyLinePattern, opcode2: Opcode.Value, transferOpcode: Opcode.Value) = {
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((HasOpcode(opcode1) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesMemory) & middle & Not(HasOpcode(opcode2))).*).capture(2) ~
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(HasOpcode(opcode2) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ (AssemblyLine.implied(transferOpcode) :: ctx.get[List[AssemblyLine]](3))
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}
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}
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private def TwoIdenticalLoadsWithNoFlagChangeInBetween(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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(HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesMemory) & DoesntChangeIndexingInAddrMode(0) & middle & Not(ChangesNAndZ)).* ~
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(HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~~> { c =>
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c.init
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}
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}
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private def TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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(HasOpcode(opcode) & HasAddrMode(Immediate) & MatchParameter(1)) ~
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(Linear & middle & Not(ChangesNAndZ)).* ~
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(HasOpcode(opcode) & Elidable & HasAddrMode(Immediate) & MatchParameter(1)) ~~> { c =>
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c.init
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}
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}
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private def TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(opcode: Opcode.Value, middle: AssemblyLinePattern) = {
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((HasOpcode(opcode) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Linear & Not(ChangesMemory) & DoesntChangeIndexingInAddrMode(0) & middle).*).capture(2) ~
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(HasOpcode(opcode) & Elidable & MatchAddrMode(0) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ ctx.get[List[AssemblyLine]](3)
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}
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}
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//noinspection ZeroIndexToHead
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private def InterleavedLoads(load: Opcode.Value, store: Opcode.Value) = {
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(Elidable & HasOpcode(load) & MatchAddrMode(0) & MatchParameter(1)).capture(12) ~
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(Elidable & HasOpcode(store) & MatchAddrMode(20) & MatchParameter(21)).+.capture(10) ~
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(Elidable & HasOpcode(load) & MatchAddrMode(2) & MatchParameter(3) & DoesNotConcernMemoryAt(0, 1) & DoesNotConcernMemoryAt(20, 21)).capture(13) ~
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(Elidable & HasOpcode(store) & DoesNotConcernMemoryAt(0, 1) & DoesNotConcernMemoryAt(2, 3)).+.capture(11) ~
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(Elidable & HasOpcode(load) & MatchAddrMode(0) & MatchParameter(1)) ~
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WhereNoMemoryAccessOverlapBetweenTwoLineLists(10, 11) ~~> { (_, ctx) =>
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List(ctx.get[List[AssemblyLine]](13),
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ctx.get[List[AssemblyLine]](11),
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ctx.get[List[AssemblyLine]](12),
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ctx.get[List[AssemblyLine]](10)).flatten
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}
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}
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val DoubleLoadToTheSameRegister = new RuleBasedAssemblyOptimization("Double load to the same register",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWithNoFlagChangeInBetween(LAX, Not(ChangesA) & Not(ChangesX) & Not(HasOpcode(DISCARD_AF)) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalImmediateLoadsWithNoFlagChangeInBetween(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDA, Not(ChangesA) & Not(HasOpcode(DISCARD_AF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDX, Not(ChangesX) & Not(HasOpcode(DISCARD_XF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LDY, Not(ChangesY) & Not(HasOpcode(DISCARD_YF))),
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TwoIdenticalLoadsWhoseFlagsWillNotBeChecked(LAX, Not(ChangesA) & Not(ChangesX) & Not(HasOpcode(DISCARD_AF)) & Not(HasOpcode(DISCARD_XF))),
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InterleavedLoads(LDA, STA),
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InterleavedLoads(LDX, STX),
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InterleavedLoads(LDY, STY),
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)
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private def pointlessLoadAfterStore(store: Opcode.Value, load: Opcode.Value, addrMode: AddrMode.Value, meantime: AssemblyLinePattern = Anything) = {
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((HasOpcode(store) & HasAddrMode(addrMode) & MatchParameter(1)) ~
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(LinearOrBranch & Not(ChangesA) & Not(ChangesMemory) & meantime).*).capture(2) ~
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(HasOpcode(load) & Elidable & HasAddrMode(addrMode) & MatchParameter(1)) ~
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((LinearOrLabel & Not(ReadsNOrZ) & Not(ChangesNAndZ)).* ~ ChangesNAndZ).capture(3) ~~> { (_, ctx) =>
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ctx.get[List[AssemblyLine]](2) ++ ctx.get[List[AssemblyLine]](3)
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}
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}
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val PointlessLoadAfterStore = new RuleBasedAssemblyOptimization("Pointless load after store",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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pointlessLoadAfterStore(STA, LDA, Absolute),
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pointlessLoadAfterStore(STA, LDA, AbsoluteX, Not(ChangesX)),
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pointlessLoadAfterStore(STA, LDA, AbsoluteY, Not(ChangesY)),
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pointlessLoadAfterStore(STX, LDX, Absolute),
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pointlessLoadAfterStore(STY, LDY, Absolute),
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)
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private val ShiftAddrModes = Set(ZeroPage, ZeroPageX, Absolute, AbsoluteX)
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private val ShiftOpcodes = Set(ASL, ROL, ROR, LSR)
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// LDA-SHIFT-STA is slower than just SHIFT
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// LDA-SHIFT-SHIFT-STA is equally fast as SHIFT-SHIFT, but the latter doesn't use the accumulator
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val PointessLoadingForShifting = new RuleBasedAssemblyOptimization("Pointless loading for shifting",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Not(ReadsA) & Not(OverwritesA)).* ~ OverwritesA ~~> { (code, ctx) =>
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AssemblyLine(ctx.get[Opcode.Value](2), ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) :: code.drop(3)
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},
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcodeIn(ShiftOpcodes) & HasAddrMode(Implied) & MatchOpcode(2)) ~
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(Elidable & HasOpcode(STA) & HasAddrModeIn(ShiftAddrModes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Not(ReadsA) & Not(OverwritesA)).* ~ OverwritesA ~~> { (code, ctx) =>
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val shift = AssemblyLine(ctx.get[Opcode.Value](2), ctx.get[AddrMode.Value](0), ctx.get[Constant](1))
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shift :: shift :: code.drop(4)
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}
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)
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// SHIFT-LDA is equally fast as LDA-SHIFT-STA, but can enable further optimizations doesn't use the accumulator
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// LDA-SHIFT-SHIFT-STA is equally fast as SHIFT-SHIFT, but the latter doesn't use the accumulator
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val LoadingAfterShifting = new RuleBasedAssemblyOptimization("Loading after shifting",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasOpcodeIn(ShiftOpcodes) & MatchAddrMode(0) & MatchParameter(1)) ~
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(Elidable & HasOpcode(LDA) & MatchAddrMode(0) & MatchParameter(1)) ~~> { (code, ctx) =>
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AssemblyLine(LDA, ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) ::
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AssemblyLine.implied(code.head.opcode) ::
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AssemblyLine(STA, ctx.get[AddrMode.Value](0), ctx.get[Constant](1)) ::
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code.drop(2)
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}
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)
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val UseZeropageAddressingMode = new RuleBasedAssemblyOptimization("Using zeropage addressing mode",
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needsFlowInfo = FlowInfoRequirement.NoRequirement,
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(Elidable & HasAddrMode(Absolute) & MatchParameter(0)) ~ Where(ctx => ctx.get[Constant](0).quickSimplify match {
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case NumericConstant(x, _) => (x & 0xff00) == 0
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case _ => false
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}) ~~> (code => code.head.copy(addrMode = ZeroPage) :: Nil)
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)
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val UseXInsteadOfStack = new RuleBasedAssemblyOptimization("Using X instead of stack",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(PHA) & DoesntMatterWhatItDoesWith(State.X)) ~
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(IsNotALabelUsedManyTimes & Not(ConcernsStack) & Not(ConcernsX)).capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(Elidable & HasOpcode(PLA)) ~~> (c =>
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AssemblyLine.implied(TAX) :: (c.tail.init :+ AssemblyLine.implied(TXA))
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)
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)
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val UseYInsteadOfStack = new RuleBasedAssemblyOptimization("Using Y instead of stack",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(PHA) & DoesntMatterWhatItDoesWith(State.Y)) ~
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(IsNotALabelUsedManyTimes & Not(ConcernsStack) & Not(ConcernsY)).capture(1) ~
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Where(_.isExternallyLinearBlock(1)) ~
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(Elidable & HasOpcode(PLA)) ~~> (c =>
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AssemblyLine.implied(TAY) :: (c.tail.init :+ AssemblyLine.implied(TYA))
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)
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)
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// TODO: make it more generic
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val IndexSwitchingOptimization = new RuleBasedAssemblyOptimization("Index switching optimization",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDY) & MatchAddrMode(2) & Not(ReadsX) & MatchParameter(0) & HasAddrModeIn(LdxAddrModes)) ~
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(Elidable & Linear & Not(ChangesY) & HasAddrMode(AbsoluteY) & SupportsAbsoluteX & Not(ConcernsX)) ~
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(HasOpcode(LDY) & Not(ConcernsX)) ~
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(Linear & Not(ChangesY) & Not(ConcernsX) & HasAddrModeIn(Set(AbsoluteY, IndexedY, ZeroPageY))) ~
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(Elidable & HasOpcode(LDY) & MatchAddrMode(2) & Not(ReadsX) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesY) & HasAddrMode(AbsoluteY) & SupportsAbsoluteX & Not(ConcernsX) & DoesntMatterWhatItDoesWith(State.X, State.N, State.Z)) ~~> { (code, ctx) =>
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List(
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code(0).copy(opcode = LDX),
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code(1).copy(addrMode = AbsoluteX),
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code(2),
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code(3),
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code(5).copy(addrMode = AbsoluteX))
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},
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(Elidable & HasOpcode(LDX) & MatchAddrMode(2) & Not(ReadsY) & MatchParameter(0) & HasAddrModeIn(LdyAddrModes)) ~
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(Elidable & Linear & Not(ChangesX) & HasAddrMode(AbsoluteX) & SupportsAbsoluteY & Not(ConcernsY)) ~
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(HasOpcode(LDX) & Not(ConcernsY)) ~
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(Linear & Not(ChangesX) & Not(ConcernsY) & HasAddrModeIn(Set(AbsoluteX, IndexedX, ZeroPageX, AbsoluteIndexedX))) ~
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(Elidable & HasOpcode(LDX) & MatchAddrMode(2) & Not(ReadsY) & MatchParameter(0)) ~
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(Elidable & Linear & Not(ChangesX) & HasAddrMode(AbsoluteX) & SupportsAbsoluteY & Not(ConcernsY) & DoesntMatterWhatItDoesWith(State.Y, State.N, State.Z)) ~~> { (code, ctx) =>
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List(
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code(0).copy(opcode = LDY),
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code(1).copy(addrMode = AbsoluteY),
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code(2),
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code(3),
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code(5).copy(addrMode = AbsoluteY))
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},
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)
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val LoadingBranchesOptimization = new RuleBasedAssemblyOptimization("Loading branches optimization",
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needsFlowInfo = FlowInfoRequirement.BackwardFlow,
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(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes) & DoesntMatterWhatItDoesWith(State.X)) ~
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(Linear & Not(ConcernsX) & Not(ChangesA) & Not(HasOpcode(CMP)) & (Not(ReadsA) | Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes))).*.capture(39) ~
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(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)).?.capture(40) ~
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(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
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(Elidable & HasOpcode(LDA)).capture(31) ~
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(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
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(Elidable & HasOpcode(LDA)).capture(32) ~
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(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1) & DoesntMatterWhatItDoesWith(State.A, State.X, State.N, State.Z)) ~~> { (code, ctx) =>
|
|
val ldx = List(code.head.copy(opcode = LDX))
|
|
val stx = ctx.get[List[AssemblyLine]](39).map(l => if (l.opcode == STA) l.copy(opcode = STX) else l)
|
|
val cpx = ctx.get[List[AssemblyLine]](40).map(_.copy(opcode = CPX))
|
|
val branch = ctx.get[List[AssemblyLine]](41)
|
|
val label = ctx.get[List[AssemblyLine]](42)
|
|
val loadIfJumped = ctx.get[List[AssemblyLine]](32)
|
|
val loadIfNotJumped = ctx.get[List[AssemblyLine]](31)
|
|
List(loadIfJumped, ldx, stx, cpx, branch, loadIfNotJumped, label).flatten
|
|
},
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes) & DoesntMatterWhatItDoesWith(State.Y)) ~
|
|
(Linear & Not(ConcernsY) & Not(ChangesA) & Not(HasOpcode(CMP)) & (Not(ReadsA) | Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes))).*.capture(39) ~
|
|
(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)).?.capture(40) ~
|
|
(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
|
|
(Elidable & HasOpcode(LDA)).capture(31) ~
|
|
(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
|
|
(Elidable & HasOpcode(LDA)).capture(32) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1) & DoesntMatterWhatItDoesWith(State.A, State.Y, State.N, State.Z)) ~~> { (code, ctx) =>
|
|
val ldy = List(code.head.copy(opcode = LDY))
|
|
val sty = ctx.get[List[AssemblyLine]](39).map(l => if (l.opcode == STA) l.copy(opcode = STY) else l)
|
|
val cpy = ctx.get[List[AssemblyLine]](40).map(_.copy(opcode = CPY))
|
|
val branch = ctx.get[List[AssemblyLine]](41)
|
|
val label = ctx.get[List[AssemblyLine]](42)
|
|
val loadIfJumped = ctx.get[List[AssemblyLine]](32)
|
|
val loadIfNotJumped = ctx.get[List[AssemblyLine]](31)
|
|
List(loadIfJumped, ldy, sty, cpy, branch, loadIfNotJumped, label).flatten
|
|
},
|
|
(HasOpcode(LDA) & Not(ConcernsX) & DoesntMatterWhatItDoesWith(State.X)) ~
|
|
(Linear & Not(ConcernsX)).*.capture(39) ~
|
|
(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes)).capture(31) ~
|
|
(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes)).capture(32) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(StxAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.X, State.N, State.Z)).capture(33) ~~> { (code, ctx) =>
|
|
val lda = List(code.head)
|
|
val cmp = ctx.get[List[AssemblyLine]](39)
|
|
val branch = ctx.get[List[AssemblyLine]](41)
|
|
val label = ctx.get[List[AssemblyLine]](42)
|
|
val loadIfJumped = ctx.get[List[AssemblyLine]](32).map(_.copy(opcode = LDX))
|
|
val loadIfNotJumped = ctx.get[List[AssemblyLine]](31).map(_.copy(opcode = LDX))
|
|
val stx = ctx.get[List[AssemblyLine]](33).map(_.copy(opcode = STX))
|
|
List(loadIfJumped, lda, cmp, branch, loadIfNotJumped, label, stx).flatten
|
|
},
|
|
(HasOpcode(LDA) & Not(ConcernsY) & DoesntMatterWhatItDoesWith(State.Y)) ~
|
|
(Linear & Not(ConcernsY)).*.capture(39) ~
|
|
(Elidable & HasOpcodeIn(OpcodeClasses.ShortConditionalBranching) & MatchParameter(22)).capture(41) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes)).capture(31) ~
|
|
(Elidable & HasOpcodeIn(Set(JMP, BRA)) & MatchParameter(21)) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(22)).capture(42) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes)).capture(32) ~
|
|
(Elidable & HasOpcode(LABEL) & MatchParameter(21) & HasCallerCount(1)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(StyAddrModes) & DoesntMatterWhatItDoesWith(State.A, State.Y, State.N, State.Z)).capture(33) ~~> { (code, ctx) =>
|
|
val lda = List(code.head)
|
|
val cmp = ctx.get[List[AssemblyLine]](39)
|
|
val branch = ctx.get[List[AssemblyLine]](41)
|
|
val label = ctx.get[List[AssemblyLine]](42)
|
|
val loadIfJumped = ctx.get[List[AssemblyLine]](32).map(_.copy(opcode = LDY))
|
|
val loadIfNotJumped = ctx.get[List[AssemblyLine]](31).map(_.copy(opcode = LDY))
|
|
val sty = ctx.get[List[AssemblyLine]](33).map(_.copy(opcode = STY))
|
|
List(loadIfJumped, lda, cmp, branch, loadIfNotJumped, label, sty).flatten
|
|
},
|
|
)
|
|
|
|
val IncreaseWithLimit = new RuleBasedAssemblyOptimization("Increase with a limit",
|
|
needsFlowInfo = FlowInfoRequirement.BackwardFlow,
|
|
(Elidable & HasOpcode(INC) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)) ~
|
|
(HasOpcode(BNE) & MatchParameter(14831)) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdyAddrModes)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.A, State.Y)) ~
|
|
(HasOpcode(LABEL) & MatchParameter(14831)) ~~> { code =>
|
|
List(
|
|
code(1).copy(opcode = LDY),
|
|
AssemblyLine.implied(INY),
|
|
code(2).copy(opcode = CPY),
|
|
code(3),
|
|
code(4).copy(opcode = LDY),
|
|
code(6),
|
|
code(5).copy(opcode = STY))
|
|
},
|
|
(Elidable & HasOpcode(INC) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(CMP) & HasAddrModeIn(CpxyAddrModes)) ~
|
|
(HasOpcode(BNE) & MatchParameter(14831)) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(LdxAddrModes)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Set(Absolute, ZeroPage)) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.A, State.X)) ~
|
|
(HasOpcode(LABEL) & MatchParameter(14831)) ~~> { code =>
|
|
List(
|
|
code(1).copy(opcode = LDX),
|
|
AssemblyLine.implied(INX),
|
|
code(2).copy(opcode = CPX),
|
|
code(3),
|
|
code(4).copy(opcode = LDX),
|
|
code(6),
|
|
code(5).copy(opcode = STX))
|
|
},
|
|
)
|
|
|
|
val UseBit = new RuleBasedAssemblyOptimization("Using BIT instruction",
|
|
needsFlowInfo = FlowInfoRequirement.BackwardFlow,
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage))) ~
|
|
(Elidable & HasOpcode(AND) & HasImmediate(0x40)) ~
|
|
(Elidable & HasOpcode(BNE) & DoesntMatterWhatItDoesWith(State.A, State.V, State.Z, State.N)) ~~> (code => List(
|
|
code.head.copy(opcode = BIT),
|
|
code.last.copy(opcode = BVS)
|
|
)),
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage))) ~
|
|
(Elidable & HasOpcode(AND) & HasImmediate(0x40)) ~
|
|
(Elidable & HasOpcode(BEQ) & DoesntMatterWhatItDoesWith(State.A, State.V, State.Z, State.N)) ~~> (code => List(
|
|
code.head.copy(opcode = BIT),
|
|
code.last.copy(opcode = BVC)
|
|
)),
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Set(Absolute, ZeroPage))) ~
|
|
(Elidable & HasOpcodeIn(Set(BMI, BPL)) & DoesntMatterWhatItDoesWith(State.A, State.V, State.Z, State.N)) ~~> (code => List(
|
|
code.head.copy(opcode = BIT),
|
|
code.last
|
|
)),
|
|
)
|
|
|
|
val ReplaceableLoad = new RuleBasedAssemblyOptimization("Replaceable load",
|
|
needsFlowInfo = FlowInfoRequirement.BothFlows,
|
|
(Elidable & HasOpcode(LDA) & MatchImmediate(1) & MatchA(0) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => Nil),
|
|
(Elidable & HasOpcode(LDX) & MatchImmediate(1) & MatchX(0) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => Nil),
|
|
(Elidable & HasOpcode(LDY) & MatchImmediate(1) & MatchY(0) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => Nil),
|
|
(Elidable & HasOpcode(LDA) & MatchImmediate(1) & MatchX(0)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => List(AssemblyLine.implied(TXA))),
|
|
(Elidable & HasOpcode(LDA) & MatchImmediate(1) & MatchY(0)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => List(AssemblyLine.implied(TYA))),
|
|
(Elidable & HasOpcode(LDX) & MatchImmediate(1) & MatchA(0)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => List(AssemblyLine.implied(TAX))),
|
|
(Elidable & HasOpcode(LDY) & MatchImmediate(1) & MatchA(0)) ~
|
|
Where(ctx => ctx.get[Constant](1).quickSimplify.isLowestByteAlwaysEqual(ctx.get[Int](0))) ~~> (_ => List(AssemblyLine.implied(TAY))),
|
|
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~
|
|
(Elidable & HasOpcode(TAX)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & DoesntMatterWhatItDoesWith(State.A)) ~~>{ code =>
|
|
List(code.head.copy(opcode = LDX), code.last.copy(opcode = STX))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~
|
|
(Elidable & HasOpcode(TAY)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & DoesntMatterWhatItDoesWith(State.A)) ~~>{ code =>
|
|
List(code.head.copy(opcode = LDY), code.last.copy(opcode = STY))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDX) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~
|
|
(Elidable & HasOpcode(TXA)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & DoesntMatterWhatItDoesWith(State.A)) ~~>{ code =>
|
|
List(code.head, code.last.copy(opcode = STX))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDY) & HasAddrModeIn(Absolute, ZeroPage, Immediate)) ~
|
|
(Elidable & HasOpcode(TYA)) ~
|
|
(Elidable & HasOpcode(STA) & HasAddrModeIn(Absolute, ZeroPage) & DoesntMatterWhatItDoesWith(State.A)) ~~>{ code =>
|
|
List(code.head, code.last.copy(opcode = STY))
|
|
},
|
|
|
|
(Elidable & HasOpcode(CMP) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDA) & MatchParameter(0) & MatchAddrMode(1) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~>{ code =>
|
|
code.init
|
|
},
|
|
(Elidable & HasOpcode(CPX) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDX) & MatchParameter(0) & MatchAddrMode(1) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~>{ code =>
|
|
code.init
|
|
},
|
|
(Elidable & HasOpcode(CPY) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDY) & MatchParameter(0) & MatchAddrMode(1) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~~>{ code =>
|
|
code.init
|
|
},
|
|
|
|
(Elidable & HasOpcode(CMP) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDX) & MatchParameter(0) & MatchAddrMode(1)) ~~>{ code =>
|
|
code.init :+ AssemblyLine.implied(TAX).pos(code.last.source)
|
|
},
|
|
(Elidable & HasOpcode(CMP) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE) & IsNotALabelUsedManyTimes) ~
|
|
(Elidable & HasOpcode(LDY) & MatchParameter(0) & MatchAddrMode(1)) ~~>{ code =>
|
|
code.init :+ AssemblyLine.implied(TAY).pos(code.last.source)
|
|
},
|
|
(Elidable & HasOpcode(CPX) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDA) & MatchParameter(0) & MatchAddrMode(1)) ~~>{ code =>
|
|
code.init :+ AssemblyLine.implied(TXA).pos(code.last.source)
|
|
},
|
|
(Elidable & HasOpcode(CPY) & MatchParameter(0) & MatchAddrMode(1)) ~
|
|
(Elidable & HasOpcode(BNE)) ~
|
|
(Elidable & HasOpcode(LDA) & MatchParameter(0) & MatchAddrMode(1)) ~~>{ code =>
|
|
code.init :+ AssemblyLine.implied(TYA).pos(code.last.source)
|
|
},
|
|
|
|
((HasOpcode(STA) & HasAddrModeIn(Absolute, LongAbsolute, ZeroPage) & MatchAddrMode(0) & MatchParameter(1)) ~
|
|
(Linear & DoesntChangeMemoryAt(0, 1) & Not(ChangesA)).*).capture(4) ~
|
|
(Elidable & HasOpcode(LDA) & DoesntMatterWhatItDoesWith(State.N, State.Z) & MatchAddrMode(2) & MatchParameter(3)).capture(66) ~
|
|
((Linear & DoesntChangeMemoryAt(0, 1) & DoesntChangeMemoryAt(2, 3) & DoesntChangeIndexingInAddrMode(2) & Not(ConcernsA)).*).capture(5) ~
|
|
(Elidable & HasOpcodeIn(ADC, ORA, EOR, AND) & HasAddrModeIn(Absolute, LongAbsolute, ZeroPage) & MatchParameter(1)) ~~> { (code, ctx) =>
|
|
ctx.get[List[AssemblyLine]](4) ++ ctx.get[List[AssemblyLine]](5) ++ ctx.get[List[AssemblyLine]](66).map(_.copy(opcode = code.last.opcode))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDA) & HasClear(State.D)) ~
|
|
(Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~
|
|
(Elidable & HasOpcode(BMI) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(LDA) & HasImmediate(0)) ~
|
|
(Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
|
|
List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDA) & HasClear(State.D) & HasY(0)) ~
|
|
(Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~
|
|
(Elidable & HasOpcode(BMI) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(TYA) & HasY(0)) ~
|
|
(Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
|
|
List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LDA) & HasClear(State.D) & HasX(0)) ~
|
|
(Elidable & HasOpcode(ORA) & HasImmediate(0x7f)) ~
|
|
(Elidable & HasOpcode(BMI) & MatchParameter(0)) ~
|
|
(Elidable & HasOpcode(TXA) & HasX(0)) ~
|
|
(Elidable & IsNotALabelUsedManyTimes & HasOpcode(LABEL) & MatchParameter(0) & DoesntMatterWhatItDoesWith(State.C, State.V)) ~~> { (code, ctx) =>
|
|
List(AssemblyLine.immediate(LDA, 0x7f), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7f))
|
|
},
|
|
)
|
|
|
|
val DontUseIndexRegisters = new RuleBasedAssemblyOptimization("Don't use index registers unnecessarily",
|
|
needsFlowInfo = FlowInfoRequirement.BackwardFlow,
|
|
|
|
(Elidable & HasOpcode(LDX) & Not(HasAddrMode(ZeroPageY)) & MatchAddrMode(0) & MatchParameter(1)) ~
|
|
(Elidable & Linear & Not(ConcernsX) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).*.captureLength(2) ~
|
|
(Elidable & HasOpcode(STX) & Not(HasAddrMode(ZeroPageY)) & DoesntMatterWhatItDoesWith(State.A, State.X)) ~~> { (code, ctx) =>
|
|
val length = ctx.get[Int](2)
|
|
code.tail.take(length) ++ (code(0).copy(opcode = LDA) :: code(length + 1).copy(opcode = STA) :: code.drop(length + 2))
|
|
},
|
|
(Elidable & HasOpcode(LDY) & Not(HasAddrMode(ZeroPageY)) & MatchAddrMode(0) & MatchParameter(1)) ~
|
|
(Elidable & Linear & Not(ConcernsY) & DoesntChangeMemoryAt(0, 1) & DoesntChangeIndexingInAddrMode(0)).*.captureLength(2) ~
|
|
(Elidable & HasOpcode(STY) & DoesntMatterWhatItDoesWith(State.A, State.Y)) ~~> { (code, ctx) =>
|
|
val length = ctx.get[Int](2)
|
|
code.tail.take(length) ++ (code(0).copy(opcode = LDA) :: code(length + 1).copy(opcode = STA) :: code.drop(length + 2))
|
|
},
|
|
|
|
(Elidable & HasOpcode(LAX) & Not(HasAddrMode(ZeroPageY))) ~
|
|
(Elidable & Linear & Not(ConcernsX) & Not(ChangesA)).*.captureLength(2) ~
|
|
(Elidable & HasOpcode(STX) & Not(HasAddrMode(ZeroPageY)) & DoesntMatterWhatItDoesWith(State.X)) ~~> { (code, ctx) =>
|
|
val length = ctx.get[Int](2)
|
|
(code(0).copy(opcode = LDA) :: code.tail.take(length)) ++ (code(length + 1).copy(opcode = STA) :: code.drop(length + 2))
|
|
},
|
|
|
|
(HasOpcode(TXA) ~
|
|
(Linear & Not(ChangesA) & Not(ChangesX) & Not(HasOpcode(TAY))).*).capture(0) ~
|
|
(Elidable & HasOpcode(TAY) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
|
(Linear & Not(ChangesX) & Not(ConcernsY)).*.capture(1) ~
|
|
(Elidable & SupportsAbsoluteX & HasAddrMode(AbsoluteY) & DoesntMatterWhatItDoesWith(State.Y)).capture(2) ~~> { (code, ctx) =>
|
|
ctx.get[List[AssemblyLine]](0) ++ ctx.get[List[AssemblyLine]](1) ++ ctx.get[List[AssemblyLine]](2).map(_.copy(addrMode = AbsoluteX))
|
|
},
|
|
|
|
(HasOpcode(TYA) ~
|
|
(Linear & Not(ChangesA) & Not(ChangesY) & Not(HasOpcode(TAX))).*).capture(0) ~
|
|
(Elidable & HasOpcode(TAX) & DoesntMatterWhatItDoesWith(State.N, State.Z)) ~
|
|
(Linear & Not(ChangesY) & Not(ConcernsX)).*.capture(1) ~
|
|
(Elidable & SupportsAbsoluteY & HasAddrMode(AbsoluteX) & DoesntMatterWhatItDoesWith(State.X)).capture(2) ~~> { (code, ctx) =>
|
|
ctx.get[List[AssemblyLine]](0) ++ ctx.get[List[AssemblyLine]](1) ++ ctx.get[List[AssemblyLine]](2).map(_.copy(addrMode = AbsoluteY))
|
|
},
|
|
|
|
)
|
|
|
|
val CommutativeInPlaceModifications = new RuleBasedAssemblyOptimization("Commutative in-place modifications",
|
|
needsFlowInfo = FlowInfoRequirement.NoRequirement,
|
|
|
|
(Elidable & HasOpcode(LDY) & HasAddrModeIn(Immediate, Absolute, ZeroPage, LongAbsolute, AbsoluteX, ZeroPageX) & MatchAddrMode(0) & MatchParameter(1)) ~
|
|
(Elidable & HasOpcode(LDA) & HasAddrModeIn(AbsoluteY, IndexedY, LongIndexedY)) ~
|
|
(Elidable & HasOpcode(LDY) & HasAddrModeIn(Immediate, Absolute, ZeroPage, LongAbsolute, AbsoluteX, ZeroPageX)) ~
|
|
(Elidable & HasOpcodeIn(ORA, EOR, AND) & HasAddrModeIn(AbsoluteY, IndexedY, LongIndexedY)) ~
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|
(Elidable & HasOpcode(LDY) & HasAddrModeIn(Immediate, Absolute, ZeroPage, LongAbsolute, AbsoluteX, ZeroPageX) & MatchAddrMode(0) & MatchParameter(1)) ~
|
|
(HasOpcodeIn(INY, DEY)).* ~
|
|
(HasOpcode(STA) & HasAddrModeIn(AbsoluteY, IndexedY, LongIndexedY)) ~~> { code =>
|
|
List(code(2), code(3).copy(opcode = LDA), code(5), code(1).copy(opcode = code(3).opcode)) ++ code.drop(5)
|
|
},
|
|
|
|
)
|
|
|
|
val BranchlessSignExtension = new RuleBasedAssemblyOptimization("Branchless sign extension",
|
|
needsFlowInfo = FlowInfoRequirement.BothFlows,
|
|
(NotFixed & HasOpcode(LDA) & HasAddrModeIn(Absolute, ZeroPage, AbsoluteX, IndexedX, IndexedY, AbsoluteY, ZeroPageX) & HasClear(State.D)) ~
|
|
(Elidable & HasOpcode(ORA) & HasImmediate(0x7F)) ~
|
|
(Elidable & HasOpcode(BMI) & MatchParameter(10)) ~
|
|
(Elidable & HasOpcode(LDA) & HasImmediate(0)) ~
|
|
(Elidable & HasOpcode(LABEL) & IsNotALabelUsedManyTimes & MatchParameter(10) & DoesntMatterWhatItDoesWith(State.V)) ~~> { code =>
|
|
List(AssemblyLine.immediate(LDA, 0x7F), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7F))
|
|
},
|
|
|
|
(NotFixed & HasOpcode(LDA) & HasAddrModeIn(Absolute, ZeroPage, AbsoluteX, IndexedX, IndexedY, AbsoluteY, ZeroPageX) & HasClear(State.D)) ~
|
|
(Elidable & HasOpcode(AND) & HasImmediate(0x80)) ~
|
|
(Elidable & HasOpcode(BPL) & MatchParameter(10)) ~
|
|
(Elidable & HasOpcode(LDA) & HasImmediate(0xff)) ~
|
|
(Elidable & HasOpcode(LABEL) & IsNotALabelUsedManyTimes & MatchParameter(10) & DoesntMatterWhatItDoesWith(State.V)) ~~> { code =>
|
|
List(AssemblyLine.immediate(LDA, 0x7F), code.head.copy(opcode = CMP), AssemblyLine.immediate(SBC, 0x7F))
|
|
},
|
|
|
|
)
|
|
|
|
// AssemblyLine.immediate(ORA, 0x7F),
|
|
// AssemblyLine.relative(BMI, label),
|
|
// AssemblyLine.immediate(LDA, 0),
|
|
// AssemblyLine.label(label))
|
|
|
|
// use the lists in OptimizationPresets to actually add these to the normal pipeline
|
|
val All = List(
|
|
BranchlessSignExtension,
|
|
CommutativeInPlaceModifications,
|
|
DontUseIndexRegisters,
|
|
DoubleLoadToDifferentRegisters,
|
|
DoubleLoadToTheSameRegister,
|
|
IndexSwitchingOptimization,
|
|
LoadingBranchesOptimization,
|
|
PointlessLoadAfterStore,
|
|
PointessLoadingForShifting,
|
|
ReplaceableLoad,
|
|
LoadingAfterShifting,
|
|
UseBit,
|
|
UseXInsteadOfStack,
|
|
UseYInsteadOfStack,
|
|
UseZeropageAddressingMode)
|
|
}
|
|
|