Add example for no_std support

.gitignore

@@ -52,7 +52,6 @@
 .settings/
 .valgrindrc
 /*-*-*-*/
-/*-*-*/
 /Makefile
 /doc
 target/

.travis.yml

@@ -1,10 +1,21 @@
 language: rust
+
+cache: cargo
 rust:
   - stable
   - beta
   - nightly
+
 matrix:
   allow_failures:
     - rust: nightly
   fast_finish: true
 
+install:
+  - rustup component add rust-src
+  - rustup target add thumbv7m-none-eabi
+
+script:
+  - cargo build
+  - cargo test
+  - cd no-std-example && cargo build

README.md

@@ -6,7 +6,7 @@ An emulator for the [MOS 6502 CPU](https://en.wikipedia.org/wiki/MOS_Technology_
 This started off as a fork of [6502-rs](https://github.com/amw-zero/6502-rs),
 which seems to be unmaintained at this point.
 
-It builds with the latest stable Rust and supports `#[no_std]` targets.
+It builds with the latest stable Rust and supports `#[no_std]` targets. (See `no-std-example` folder for more info.)
 
 ## Usage example
 

no-std-example/.cargo/config

@@ -0,0 +1,33 @@
+[target.thumbv7m-none-eabi]
+# uncomment this to make `cargo run` execute programs on QEMU
+# runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel"
+
+[target.'cfg(all(target_arch = "arm", target_os = "none"))']
+# uncomment ONE of these three option to make `cargo run` start a GDB session
+# which option to pick depends on your system
+# runner = "arm-none-eabi-gdb -q -x openocd.gdb"
+# runner = "gdb-multiarch -q -x openocd.gdb"
+# runner = "gdb -q -x openocd.gdb"
+
+rustflags = [
+  # LLD (shipped with the Rust toolchain) is used as the default linker
+  "-C", "link-arg=-Tlink.x",
+
+  # if you run into problems with LLD switch to the GNU linker by commenting out
+  # this line
+  # "-C", "linker=arm-none-eabi-ld",
+
+  # if you need to link to pre-compiled C libraries provided by a C toolchain
+  # use GCC as the linker by commenting out both lines above and then
+  # uncommenting the three lines below
+  # "-C", "linker=arm-none-eabi-gcc",
+  # "-C", "link-arg=-Wl,-Tlink.x",
+  # "-C", "link-arg=-nostartfiles",
+]
+
+[build]
+# Pick ONE of these compilation targets
+# target = "thumbv6m-none-eabi"    # Cortex-M0 and Cortex-M0+
+target = "thumbv7m-none-eabi"    # Cortex-M3
+# target = "thumbv7em-none-eabi"   # Cortex-M4 and Cortex-M7 (no FPU)
+# target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)

no-std-example/.gitignore

@@ -0,0 +1,5 @@
+**/*.rs.bk
+.#*
+.gdb_history
+Cargo.lock
+target/

no-std-example/Cargo.toml

@@ -0,0 +1,35 @@
+[package]
+authors = ["Matthias Endler <matthias-endler@gmx.net>"]
+edition = "2018"
+readme = "README.md"
+name = "no-std-example"
+version = "0.1.0"
+
+[dependencies]
+cortex-m = "0.5.7"
+cortex-m-rt = "0.6.3"
+cortex-m-semihosting = "0.3.1"
+panic-halt = "0.2.0"
+mos6502 = { path = ".." }
+
+# Uncomment for the panic example.
+# panic-itm = "0.4.0"
+
+# Uncomment for the allocator example.
+# alloc-cortex-m = "0.3.5"
+
+# Uncomment for the device example.
+# [dependencies.stm32f30x]
+# features = ["rt"]
+# version = "0.7.1"
+
+# this lets you use `cargo fix`!
+[[bin]]
+name = "no-std-example"
+test = false
+bench = false
+
+[profile.release]
+codegen-units = 1 # better optimizations
+debug = true # symbols are nice and they don't increase the size on Flash
+lto = true # better optimizations

no-std-example/README.md

@@ -0,0 +1,2 @@
+This is a sample project demonstrating how to use the [mos602](https://github.com/mre/mos6502) crate on `#[no_std]` devices.
+It was bootstrapped using the awesome [`cortex-m-quickstart`](https://github.com/rust-embedded/cortex-m-quickstart) template.

no-std-example/build.rs

@@ -0,0 +1,18 @@
+use std::env;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+
+fn main() {
+    // Put the linker script somewhere the linker can find it
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("memory.x"))
+        .unwrap()
+        .write_all(include_bytes!("memory.x"))
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+
+    // Only re-run the build script when memory.x is changed,
+    // instead of when any part of the source code changes.
+    println!("cargo:rerun-if-changed=memory.x");
+}

no-std-example/memory.x

@@ -0,0 +1,34 @@
+MEMORY
+{
+  /* NOTE 1 K = 1 KiBi = 1024 bytes */
+  /* TODO Adjust these memory regions to match your device memory layout */
+  /* These values correspond to the LM3S6965, one of the few devices QEMU can emulate */
+  FLASH : ORIGIN = 0x00000000, LENGTH = 256K
+  RAM : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* This is where the call stack will be allocated. */
+/* The stack is of the full descending type. */
+/* You may want to use this variable to locate the call stack and static
+   variables in different memory regions. Below is shown the default value */
+/* _stack_start = ORIGIN(RAM) + LENGTH(RAM); */
+
+/* You can use this symbol to customize the location of the .text section */
+/* If omitted the .text section will be placed right after the .vector_table
+   section */
+/* This is required only on microcontrollers that store some configuration right
+   after the vector table */
+/* _stext = ORIGIN(FLASH) + 0x400; */
+
+/* Example of putting non-initialized variables into custom RAM locations. */
+/* This assumes you have defined a region RAM2 above, and in the Rust
+   sources added the attribute `#[link_section = ".ram2bss"]` to the data
+   you want to place there. */
+/* Note that the section will not be zero-initialized by the runtime! */
+/* SECTIONS {
+     .ram2bss (NOLOAD) : ALIGN(4) {
+       *(.ram2bss);
+       . = ALIGN(4);
+     } > RAM2
+   } INSERT AFTER .bss;
+*/

no-std-example/openocd.cfg

@@ -0,0 +1,12 @@
+# Sample OpenOCD configuration for the STM32F3DISCOVERY development board
+
+# Depending on the hardware revision you got you'll have to pick ONE of these
+# interfaces. At any time only one interface should be commented out.
+
+# Revision C (newer revision)
+source [find interface/stlink-v2-1.cfg]
+
+# Revision A and B (older revisions)
+# source [find interface/stlink-v2.cfg]
+
+source [find target/stm32f3x.cfg]

no-std-example/openocd.gdb

@@ -0,0 +1,32 @@
+target extended-remote :3333
+
+# print demangled symbols
+set print asm-demangle on
+
+# detect unhandled exceptions, hard faults and panics
+break DefaultHandler
+break UserHardFault
+break rust_begin_unwind
+
+# *try* to stop at the user entry point (it might be gone due to inlining)
+break main
+
+monitor arm semihosting enable
+
+# # send captured ITM to the file itm.fifo
+# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
+# # 8000000 must match the core clock frequency
+# monitor tpiu config internal itm.txt uart off 8000000
+
+# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
+# # 8000000 must match the core clock frequency
+# # 2000000 is the frequency of the SWO pin
+# monitor tpiu config external uart off 8000000 2000000
+
+# # enable ITM port 0
+# monitor itm port 0 on
+
+load
+
+# start the process but immediately halt the processor
+stepi

no-std-example/src/main.rs

@@ -0,0 +1,82 @@
+#![no_std]
+#![no_main]
+
+// you can put a breakpoint on `rust_begin_unwind` to catch panics
+extern crate panic_halt;
+
+extern crate mos6502;
+
+use cortex_m_rt::entry;
+use mos6502::address::Address;
+use mos6502::cpu;
+
+#[entry]
+fn main() -> ! {
+	loop {
+		let mut cpu = cpu::CPU::new();
+
+		let zero_page_data = [
+			// ZeroPage data start
+			0x00, 0x02, // ADC ZeroPage target
+			0x00, 0x04, // ADC ZeroPageX target
+			0x00, 0x00, 0x00, 0x00, 0x10, // ADC IndexedIndirectX address
+			0x80, // ADC IndexedIndirectX address
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x08, // ADC IndirectIndexedY address
+			0x80, // ADC IndirectIndexedY address
+		];
+
+		let program = [
+			// Code start
+			0xA9, // LDA Immediate
+			0x01, //     Immediate operand
+			0x69, // ADC Immediate
+			0x07, //     Immediate operand
+			0x65, // ADC ZeroPage
+			0x01, //     ZeroPage operand
+			0xA2, // LDX Immediate
+			0x01, //     Immediate operand
+			0x75, // ADC ZeroPageX
+			0x02, //     ZeroPageX operand
+			0x6D, // ADC Absolute
+			0x01, //     Absolute operand
+			0x80, //     Absolute operand
+			0xA2, // LDX immediate
+			0x08, //     Immediate operand
+			0x7D, // ADC AbsoluteX
+			0x00, //     AbsoluteX operand
+			0x80, //     AbsoluteX operand
+			0xA0, // LDY immediate
+			0x04, //     Immediate operand
+			0x79, // ADC AbsoluteY
+			0x00, //     AbsoluteY operand
+			0x80, //     AbsoluteY operand
+			0xA2, // LDX immediate
+			0x05, //     Immediate operand
+			0x61, // ADC IndexedIndirectX
+			0x03, //     IndexedIndirectX operand
+			0xA0, // LDY immediate
+			0x10, //     Immediate operand
+			0x71, // ADC IndirectIndexedY
+			0x0F, //     IndirectIndexedY operand
+			0xEA, // NOP :)
+			0xFF, // Something invalid -- the end!
+		];
+
+		let data: [u8; 25] = [
+			0x00, 0x09, // ADC Absolute target
+			0x00, 0x00, 0x40, // ADC AbsoluteY target
+			0x00, 0x00, 0x00, 0x11, // ADC AbsoluteX target
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, // ADC IndexedIndirectX target
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, // ADC IndirectIndexedY target
+		];
+
+		// "Load" a program
+		cpu.memory.set_bytes(Address(0x0000), &zero_page_data);
+		cpu.memory.set_bytes(Address(0x4000), &program);
+		cpu.memory.set_bytes(Address(0x8000), &data);
+
+		cpu.registers.program_counter = Address(0x4000);
+
+		cpu.run();
+	}
+}