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implement stz
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@ -593,6 +593,9 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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(Instruction::STY, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, self.registers.index_y);
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}
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(Instruction::STZ, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, 0);
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}
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(Instruction::TAX, OpInput::UseImplied) => {
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let val = self.registers.accumulator;
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@ -100,6 +100,7 @@ pub enum Instruction {
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STA, // STore Accumulator............. | .. ..... M = A
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STX, // STore X register.............. | .. ..... M = X
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STY, // STore Y register.............. | .. ..... M = Y
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STZ, // STore Zero.................... | .. ..... M = Y
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TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
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TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
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TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
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@ -499,6 +500,10 @@ impl crate::Variant for Cmos6502 {
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0x3a => Some((Instruction::DEC, AddressingMode::Accumulator)),
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0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
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0x80 => Some((Instruction::BRA, AddressingMode::Relative)),
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0x64 => Some((Instruction::STZ, AddressingMode::ZeroPage)),
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0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)),
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0x9c => Some((Instruction::STZ, AddressingMode::Absolute)),
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0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)),
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_ => Nmos6502::decode(opcode),
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}
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}
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