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Cmos support (#99)
This commit is contained in:
omarandlorraine
GitHub
parent
467b3ff436
commit
265ef6941e
110
src/cpu.rs
110
src/cpu.rs
@ -212,6 +212,14 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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)
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}
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AddressingMode::ZeroPageIndirect => {
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// Use [u8, ..1] from instruction
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// This is where the absolute (16-bit) target address is stored.
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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};
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// Increment program counter
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@ -286,6 +294,16 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.branch_if_not_equal(addr);
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}
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(Instruction::BIT, OpInput::UseImmediate(val)) => {
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::BIT, OpInput::UseAddress(addr)) => {
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let a: u8 = self.registers.accumulator;
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let m: u8 = self.memory.get_byte(addr);
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@ -322,6 +340,11 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.branch_if_positive(addr);
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}
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(Instruction::BRA, OpInput::UseRelative(rel)) => {
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let addr = self.registers.program_counter.wrapping_add(rel);
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self.branch(addr);
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}
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(Instruction::BRK, OpInput::UseImplied) => {
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for b in self.registers.program_counter.wrapping_sub(1).to_be_bytes() {
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self.push_on_stack(b);
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@ -333,6 +356,18 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.registers.status.or(Status::PS_DISABLE_INTERRUPTS);
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}
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(Instruction::BRKcld, OpInput::UseImplied) => {
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for b in self.registers.program_counter.wrapping_sub(1).to_be_bytes() {
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self.push_on_stack(b);
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}
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self.push_on_stack(self.registers.status.bits());
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let pcl = self.memory.get_byte(0xfffe);
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let pch = self.memory.get_byte(0xffff);
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self.jump((u16::from(pch) << 8) | u16::from(pcl));
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self.registers.status.or(Status::PS_DISABLE_INTERRUPTS);
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self.registers.status.and(!Status::PS_DECIMAL_MODE);
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}
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(Instruction::BVC, OpInput::UseRelative(rel)) => {
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let addr = self.registers.program_counter.wrapping_add(rel);
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self.branch_if_overflow_clear(addr);
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@ -478,11 +513,47 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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let val = self.registers.accumulator;
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self.push_on_stack(val);
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}
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(Instruction::PHX, OpInput::UseImplied) => {
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// Push X
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self.push_on_stack(self.registers.index_x);
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}
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(Instruction::PHY, OpInput::UseImplied) => {
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// Push Y
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self.push_on_stack(self.registers.index_y);
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}
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(Instruction::PHP, OpInput::UseImplied) => {
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// Push status
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let val = self.registers.status.bits() | 0x30;
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self.push_on_stack(val);
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}
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(Instruction::PLX, OpInput::UseImplied) => {
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// Pull accumulator
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self.pull_from_stack();
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let val: u8 = self.fetch_from_stack();
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self.registers.index_x = val;
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self.registers.status.set_with_mask(
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Status::PS_ZERO | Status::PS_NEGATIVE,
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Status::new(StatusArgs {
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zero: val == 0,
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negative: self.registers.accumulator > 127,
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::PLY, OpInput::UseImplied) => {
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// Pull accumulator
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self.pull_from_stack();
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let val: u8 = self.fetch_from_stack();
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self.registers.index_y = val;
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self.registers.status.set_with_mask(
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Status::PS_ZERO | Status::PS_NEGATIVE,
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Status::new(StatusArgs {
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zero: val == 0,
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negative: self.registers.accumulator > 127,
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::PLA, OpInput::UseImplied) => {
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// Pull accumulator
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self.pull_from_stack();
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@ -588,6 +659,9 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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(Instruction::STY, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, self.registers.index_y);
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}
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(Instruction::STZ, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, 0);
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}
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(Instruction::TAX, OpInput::UseImplied) => {
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let val = self.registers.accumulator;
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@ -597,6 +671,38 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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let val = self.registers.accumulator;
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self.load_y_register(val);
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}
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(Instruction::TRB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator set the corresponding bits in the operand
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let res = self.registers.accumulator | val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator clear the corresponding bits in the operand
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let res = (self.registers.accumulator ^ 0xff) & val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSX, OpInput::UseImplied) => {
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let StackPointer(val) = self.registers.stack_pointer;
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self.load_x_register(val);
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@ -1011,6 +1117,10 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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}
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}
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fn branch(&mut self, addr: u16) {
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self.registers.program_counter = addr;
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}
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fn branch_if_positive(&mut self, addr: u16) {
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if !self.registers.status.contains(Status::PS_NEGATIVE) {
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self.registers.program_counter = addr;
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@ -25,86 +25,208 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// Abbreviations
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//
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// General
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//
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// M | `Memory location`
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//
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// Registers
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//
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// A | accumulator
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// X | general purpose register
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// Y | general purpose register
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// F | processor status flags, collectively
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// NV-BDIZC | processor status flags, individually
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// S | stack pointer
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// PC | program counter
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//
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Instruction {
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ADC, // ADd with Carry................ | NV ...ZC A = A + M + C
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ADCnd, // ADd with Carry................ | NV ...ZC A = A + M + C
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AND, // logical AND (bitwise)......... | N. ...Z. A = A && M
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ASL, // Arithmetic Shift Left......... | N. ...ZC A = M << 1
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BCC, // Branch if Carry Clear......... | .. ..... PC = !C
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BCS, // Branch if Carry Set........... | .. ..... PC = C
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BEQ, // Branch if Equal (to zero?).... | .. ..... PC = Z
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BIT, // BIT test...................... | NV ...Z. = A & M
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BMI, // Branch if Minus............... | .. ..... PC = N
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BNE, // Branch if Not Equal........... | .. ..... PC = !Z
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BPL, // Branch if Positive............ | .. ..... PC = Z
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BRK, // BReaK......................... | .. B.... S PC =
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BVC, // Branch if oVerflow Clear...... | .. ..... PC = !V
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BVS, // Branch if oVerflow Set........ | .. ..... PC = V
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CLC, // CLear Carry flag.............. | .. ....C = 0
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CLD, // Clear Decimal Mode............ | .. .D... = 0
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CLI, // Clear Interrupt Disable....... | .. ..I.. = 0
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CLV, // Clear oVerflow flag........... | .V ..... = 0
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CMP, // Compare....................... | N. ...ZC = A - M
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CPX, // Compare X register............ | N. ...ZC = X - M
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CPY, // Compare Y register............ | N. ...ZC = Y - M
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DEC, // DECrement memory.............. | N. ...Z. M = M - 1
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DEX, // DEcrement X register.......... | N. ...Z. X = X - 1
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DEY, // DEcrement Y register.......... | N. ...Z. Y = Y - 1
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EOR, // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
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INC, // INCrement memory.............. | N. ...Z. M = M + 1
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INX, // INcrement X register.......... | N. ...Z. X = X + 1
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INY, // INcrement Y register.......... | N. ...Z. Y = Y + 1
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JMP, // JuMP.......................... | .. ..... S PC =
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JSR, // Jump to SubRoutine............ | .. ..... S PC =
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LDA, // LoaD Accumulator.............. | N. ...Z. A = M
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LDX, // LoaD X register............... | N. ...Z. X = M
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LDY, // LoaD Y register............... | N. ...Z. Y = M
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LSR, // Logical Shift Right........... | N. ...ZC A = A/2
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// or N. ...ZC M = M/2
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NOP, // No OPeration.................. | .. ..... =
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ORA, // inclusive OR (bitwise)........ | N. ...Z. A = A | M
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PHA, // PusH Accumulator.............. | .. ..... S M = A
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PHP, // PusH Processor status......... | .. ..... S M = F
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PLA, // PuLl Accumulator.............. | N. ...Z. A S = M (stack)
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PLP, // PuLl Processor status......... | NV BDIZC S = M (stack)
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ROL, // ROtate Left................... | N. ...ZC A = C A rotated
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// or N. ...ZC M = C M rotated
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ROR, // ROtate Right.................. | N. ...ZC A = C A rotated
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// or N. ...ZC M = C M rotated
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RTI, // ReTurn from Interrupt......... | NV BDIZC PC = M (stack)
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RTS, // ReTurn from Subroutine........ | .. ..... PC = M (stack)
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SBC, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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SBCnd, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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SEC, // SEt Carry flag................ | .. ....C = 1
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SED, // SEt Decimal flag.............. | .. .D... = 1
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SEI, // SEt Interrupt disable......... | .. ..I.. = 1
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STA, // STore Accumulator............. | .. ..... M = A
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STX, // STore X register.............. | .. ..... M = X
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STY, // STore Y register.............. | .. ..... M = Y
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TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
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TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
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TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
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TXA, // Transfer X to Accumulator..... | N. ...Z. A = X
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TXS, // Transfer X to Stack pointer... | .. ..... S = X
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TYA, // Transfer Y to Accumulator..... | N. ...Z. A = Y
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// ADd with Carry
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ADC,
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// ADd with Carry. This one has now decimal mode.
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ADCnd,
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// logical AND (bitwise)
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AND,
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// Arithmetic Shift Left
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ASL,
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// Branch if Carry Clear
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BCC,
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// Branch if Carry Set
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BCS,
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// Branch if Equal (to zero?)
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BEQ,
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// BIT test
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BIT,
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// Branch if Minus
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BMI,
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// Branch if Not Equal
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BNE,
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// Branch if Positive
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BPL,
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// Unconditional BRAnch
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BRA,
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// BReaK
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BRK,
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// BReaK, clearing decimal flag
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BRKcld,
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// Branch if oVerflow Clear
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BVC,
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// Branch if oVerflow Set
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BVS,
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// CLear Carry flag
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CLC,
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// Clear Decimal Mode
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CLD,
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// Clear Interrupt Disable
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CLI,
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// Clear oVerflow flag
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CLV,
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// Compare
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CMP,
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// Compare X register
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CPX,
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// Compare Y register
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CPY,
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// DECrement memory
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DEC,
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// DEcrement X register
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DEX,
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// DEcrement Y register
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DEY,
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// Exclusive OR (bitwise)
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EOR,
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// INCrement memory
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INC,
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// INcrement X register
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INX,
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// INcrement Y register
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INY,
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// JuMP
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JMP,
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// Jump to SubRoutine
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JSR,
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// LoaD Accumulator
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LDA,
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// LoaD X register
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LDX,
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// LoaD Y register
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LDY,
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// Logical Shift Right
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LSR,
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// No OPeration
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NOP,
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// inclusive OR (bitwise)
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ORA,
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// PusH Accumulator
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PHA,
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// PusH X
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PHX,
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// PusH Y
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PHY,
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// PusH Processor status
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PHP,
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// PuLl Accumulator
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PLA,
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// PuLl X
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PLX,
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// PuLl Y
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PLY,
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// PuLl Processor status
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PLP,
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// ROtate Left
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ROL,
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// ROtate Right
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ROR,
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// ReTurn from Interrupt
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RTI,
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// ReTurn from Subroutine
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RTS,
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// SuBtract with Carry
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SBC,
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// SuBtract with Carry. This one has now decimal mode.
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SBCnd,
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// SEt Carry flag
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SEC,
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// SEt Decimal flag
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SED,
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// SEt Interrupt disable
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SEI,
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// STore Accumulator
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STA,
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// STore X register
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STX,
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// STore Y register
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STY,
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// STore Zero
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STZ,
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// Transfer Accumulator to X
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TAX,
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// Transfer Accumulator to Y
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TAY,
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// Test and Reset Bits
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TRB,
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// Test and Set Bits
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TSB,
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// Transfer Stack pointer to X
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TSX,
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// Transfer X to Accumulator
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TXA,
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// Transfer X to Stack pointer
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TXS,
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// Transfer Y to Accumulator
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TYA,
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}
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#[derive(Copy, Clone, Debug)]
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@ -158,6 +280,9 @@ pub enum AddressingMode {
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// load from (address stored at constant zero page address) plus Y register, e. g. `lda ($10),Y`.
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IndirectIndexedY,
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// Address stored at constant zero page address
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ZeroPageIndirect,
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}
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impl AddressingMode {
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@ -178,6 +303,7 @@ impl AddressingMode {
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AddressingMode::BuggyIndirect => 2,
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AddressingMode::IndexedIndirectX => 1,
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AddressingMode::IndirectIndexedY => 1,
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AddressingMode::ZeroPageIndirect => 1,
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}
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}
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}
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@ -458,24 +584,15 @@ pub struct Ricoh2a03;
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impl crate::Variant for Ricoh2a03 {
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fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
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match opcode {
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0x61 => Some((Instruction::ADCnd, AddressingMode::IndexedIndirectX)),
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0x65 => Some((Instruction::ADCnd, AddressingMode::ZeroPage)),
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0x69 => Some((Instruction::ADCnd, AddressingMode::Immediate)),
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0x6d => Some((Instruction::ADCnd, AddressingMode::Absolute)),
|
||||
0x71 => Some((Instruction::ADCnd, AddressingMode::IndirectIndexedY)),
|
||||
0x75 => Some((Instruction::ADCnd, AddressingMode::ZeroPageX)),
|
||||
0x79 => Some((Instruction::ADCnd, AddressingMode::AbsoluteY)),
|
||||
0x7d => Some((Instruction::ADCnd, AddressingMode::AbsoluteX)),
|
||||
0xe1 => Some((Instruction::SBCnd, AddressingMode::IndexedIndirectX)),
|
||||
0xe5 => Some((Instruction::SBCnd, AddressingMode::ZeroPage)),
|
||||
0xe9 => Some((Instruction::SBCnd, AddressingMode::Immediate)),
|
||||
0xed => Some((Instruction::SBCnd, AddressingMode::Absolute)),
|
||||
0xf1 => Some((Instruction::SBCnd, AddressingMode::IndirectIndexedY)),
|
||||
0xf5 => Some((Instruction::SBCnd, AddressingMode::ZeroPageX)),
|
||||
0xf9 => Some((Instruction::SBCnd, AddressingMode::AbsoluteY)),
|
||||
0xfd => Some((Instruction::SBCnd, AddressingMode::AbsoluteX)),
|
||||
_ => Nmos6502::decode(opcode),
|
||||
// It's the same as on NMOS, but doesn't support decimal mode.
|
||||
match Nmos6502::decode(opcode) {
|
||||
Some((Instruction::ADC, addressing_mode)) => {
|
||||
Some((Instruction::ADCnd, addressing_mode))
|
||||
}
|
||||
Some((Instruction::SBC, addressing_mode)) => {
|
||||
Some((Instruction::SBCnd, addressing_mode))
|
||||
}
|
||||
something_else => something_else,
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -487,14 +604,10 @@ pub struct RevisionA;
|
||||
|
||||
impl crate::Variant for RevisionA {
|
||||
fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
|
||||
#[allow(clippy::match_same_arms)]
|
||||
match opcode {
|
||||
0x66 => None,
|
||||
0x6a => None,
|
||||
0x6e => None,
|
||||
0x76 => None,
|
||||
0x7e => None,
|
||||
_ => Nmos6502::decode(opcode),
|
||||
// It's the same as on NMOS, but has no ROR instruction.
|
||||
match Nmos6502::decode(opcode) {
|
||||
Some((Instruction::ROR, _)) => None,
|
||||
something_else => something_else,
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -507,7 +620,32 @@ impl crate::Variant for Cmos6502 {
|
||||
fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
|
||||
// TODO: We obviously need to add the other CMOS instructions here.
|
||||
match opcode {
|
||||
0x00 => Some((Instruction::BRKcld, AddressingMode::Implied)),
|
||||
0x1a => Some((Instruction::INC, AddressingMode::Accumulator)),
|
||||
0x3a => Some((Instruction::DEC, AddressingMode::Accumulator)),
|
||||
0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
|
||||
0x80 => Some((Instruction::BRA, AddressingMode::Relative)),
|
||||
0x64 => Some((Instruction::STZ, AddressingMode::ZeroPage)),
|
||||
0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)),
|
||||
0x9c => Some((Instruction::STZ, AddressingMode::Absolute)),
|
||||
0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)),
|
||||
0x7a => Some((Instruction::PLY, AddressingMode::Implied)),
|
||||
0xfa => Some((Instruction::PLX, AddressingMode::Implied)),
|
||||
0x5a => Some((Instruction::PHY, AddressingMode::Implied)),
|
||||
0xda => Some((Instruction::PHX, AddressingMode::Implied)),
|
||||
0x04 => Some((Instruction::TSB, AddressingMode::ZeroPage)),
|
||||
0x14 => Some((Instruction::TRB, AddressingMode::ZeroPage)),
|
||||
0x0c => Some((Instruction::TSB, AddressingMode::Absolute)),
|
||||
0x1c => Some((Instruction::TRB, AddressingMode::Absolute)),
|
||||
0x12 => Some((Instruction::ORA, AddressingMode::ZeroPageIndirect)),
|
||||
0x32 => Some((Instruction::AND, AddressingMode::ZeroPageIndirect)),
|
||||
0x52 => Some((Instruction::EOR, AddressingMode::ZeroPageIndirect)),
|
||||
0x72 => Some((Instruction::ADC, AddressingMode::ZeroPageIndirect)),
|
||||
0x92 => Some((Instruction::STA, AddressingMode::ZeroPageIndirect)),
|
||||
0xb2 => Some((Instruction::LDA, AddressingMode::ZeroPageIndirect)),
|
||||
0xd2 => Some((Instruction::CMP, AddressingMode::ZeroPageIndirect)),
|
||||
0xf2 => Some((Instruction::SBC, AddressingMode::ZeroPageIndirect)),
|
||||
0x89 => Some((Instruction::BIT, AddressingMode::Immediate)),
|
||||
_ => Nmos6502::decode(opcode),
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user