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https://github.com/mre/mos6502.git
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get rid of silly xextend function; just use the .into()
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parent
3accd8ce40
commit
7222388c5e
10
src/cpu.rs
10
src/cpu.rs
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@ -30,10 +30,6 @@ use crate::memory::Bus;
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use crate::registers::{Registers, StackPointer, Status, StatusArgs};
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use crate::registers::{Registers, StackPointer, Status, StatusArgs};
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fn xextend(x: u8) -> u16 {
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u16::from(x)
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}
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fn arr_to_addr(arr: &[u8]) -> u16 {
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fn arr_to_addr(arr: &[u8]) -> u16 {
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debug_assert!(arr.len() == 2);
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debug_assert!(arr.len() == 2);
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@ -141,12 +137,12 @@ impl<M: Bus> CPU<M> {
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AddressingMode::AbsoluteX => {
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AddressingMode::AbsoluteX => {
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// Use [u8, ..2] from instruction as address, add X
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// Use [u8, ..2] from instruction as address, add X
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// (Output: a 16-bit address)
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(x)))
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(x.into()))
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}
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}
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AddressingMode::AbsoluteY => {
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AddressingMode::AbsoluteY => {
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// Use [u8, ..2] from instruction as address, add Y
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// Use [u8, ..2] from instruction as address, add Y
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// (Output: a 16-bit address)
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(y)))
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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}
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}
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AddressingMode::Indirect => {
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AddressingMode::Indirect => {
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// Use [u8, ..2] from instruction as an address. Interpret the
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// Use [u8, ..2] from instruction as an address. Interpret the
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@ -171,7 +167,7 @@ impl<M: Bus> CPU<M> {
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// (Output: a 16-bit address)
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// (Output: a 16-bit address)
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let start = slice[0];
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(xextend(y)))
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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}
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}
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};
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};
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