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add the cmos addressing mode, indirect unindexed
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parent
747d620943
commit
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10
src/cpu.rs
10
src/cpu.rs
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@ -201,6 +201,16 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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)
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}
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AddressingMode::ZeroPageIndirect => {
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// Use [u8, ..1] from instruction
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// This is where the absolute (16-bit) target address is stored.
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(
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address_from_bytes(slice[0], slice[1])
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)
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}
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};
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// Increment program counter
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@ -280,6 +280,9 @@ pub enum AddressingMode {
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// load from (address stored at constant zero page address) plus Y register, e. g. `lda ($10),Y`.
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IndirectIndexedY,
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// Address stored at constant zero page address
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ZeroPageIndirect,
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}
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impl AddressingMode {
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@ -299,6 +302,7 @@ impl AddressingMode {
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AddressingMode::BuggyIndirect => 2,
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AddressingMode::IndexedIndirectX => 1,
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AddressingMode::IndirectIndexedY => 1,
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AddressingMode::ZeroPageIndirect => 1,
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}
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}
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}
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@ -628,6 +632,14 @@ impl crate::Variant for Cmos6502 {
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0x14 => Some((Instruction::TRB, AddressingMode::ZeroPage)),
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0x0c => Some((Instruction::TSB, AddressingMode::Absolute)),
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0x1c => Some((Instruction::TRB, AddressingMode::Absolute)),
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0x12 => Some((Instruction::ORA, AddressingMode::ZeroPageIndirect)),
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0x32 => Some((Instruction::AND, AddressingMode::ZeroPageIndirect)),
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0x52 => Some((Instruction::EOR, AddressingMode::ZeroPageIndirect)),
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0x72 => Some((Instruction::ADC, AddressingMode::ZeroPageIndirect)),
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0x92 => Some((Instruction::STA, AddressingMode::ZeroPageIndirect)),
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0xb2 => Some((Instruction::LDA, AddressingMode::ZeroPageIndirect)),
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0xd2 => Some((Instruction::CMP, AddressingMode::ZeroPageIndirect)),
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0xf2 => Some((Instruction::SBC, AddressingMode::ZeroPageIndirect)),
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_ => Nmos6502::decode(opcode),
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}
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}
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