diff --git a/src/cpu.rs b/src/cpu.rs index 45fe5ed..56eb4fb 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -471,11 +471,47 @@ impl CPU { let val = self.registers.accumulator; self.push_on_stack(val); } + (Instruction::PHX, OpInput::UseImplied) => { + // Push X + self.push_on_stack(self.registers.index_x); + } + (Instruction::PHY, OpInput::UseImplied) => { + // Push Y + self.push_on_stack(self.registers.index_y); + } (Instruction::PHP, OpInput::UseImplied) => { // Push status let val = self.registers.status.bits() | 0x30; self.push_on_stack(val); } + (Instruction::PLX, OpInput::UseImplied) => { + // Pull accumulator + self.pull_from_stack(); + let val: u8 = self.fetch_from_stack(); + self.registers.index_x = val; + self.registers.status.set_with_mask( + Status::PS_ZERO | Status::PS_NEGATIVE, + Status::new(StatusArgs { + zero: val == 0, + negative: self.registers.accumulator > 127, + ..StatusArgs::none() + }), + ); + } + (Instruction::PLY, OpInput::UseImplied) => { + // Pull accumulator + self.pull_from_stack(); + let val: u8 = self.fetch_from_stack(); + self.registers.index_y = val; + self.registers.status.set_with_mask( + Status::PS_ZERO | Status::PS_NEGATIVE, + Status::new(StatusArgs { + zero: val == 0, + negative: self.registers.accumulator > 127, + ..StatusArgs::none() + }), + ); + } (Instruction::PLA, OpInput::UseImplied) => { // Pull accumulator self.pull_from_stack(); diff --git a/src/instruction.rs b/src/instruction.rs index 8854154..3b97477 100644 --- a/src/instruction.rs +++ b/src/instruction.rs @@ -83,8 +83,12 @@ pub enum Instruction { NOP, // No OPeration.................. | .. ..... = ORA, // inclusive OR (bitwise)........ | N. ...Z. A = A | M PHA, // PusH Accumulator.............. | .. ..... S M = A + PHX, // PusH X........................ | .. ..... S M = A + PHY, // PusH Y........................ | .. ..... S M = A PHP, // PusH Processor status......... | .. ..... S M = F PLA, // PuLl Accumulator.............. | N. ...Z. A S = M (stack) + PLX, // PuLl X........................ | N. ...Z. A S = M (stack) + PLY, // PuLl Y........................ | N. ...Z. A S = M (stack) PLP, // PuLl Processor status......... | NV BDIZC S = M (stack) ROL, // ROtate Left................... | N. ...ZC A = C A rotated // or N. ...ZC M = C M rotated @@ -499,6 +503,10 @@ impl crate::Variant for Cmos6502 { 0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)), 0x9c => Some((Instruction::STZ, AddressingMode::Absolute)), 0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)), + 0x7a => Some((Instruction::PLY, AddressingMode::Implied)), + 0xfa => Some((Instruction::PLX, AddressingMode::Implied)), + 0x5a => Some((Instruction::PHY, AddressingMode::Implied)), + 0xda => Some((Instruction::PHX, AddressingMode::Implied)), _ => Nmos6502::decode(opcode), } }