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change arr_to_addr to address_from_bytes
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parent
11499b6bc8
commit
da30c8c67d
15
src/cpu.rs
15
src/cpu.rs
@ -31,10 +31,9 @@ use crate::Variant;
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use crate::registers::{Registers, StackPointer, Status, StatusArgs};
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fn arr_to_addr(arr: &[u8]) -> u16 {
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debug_assert!(arr.len() == 2);
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fn address_from_bytes(lo: u8, hi: u8) -> u16 {
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u16::from(arr[0]) + (u16::from(arr[1]) << 8usize)
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u16::from(lo) + (u16::from(hi) << 8usize)
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}
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#[derive(Clone)]
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@ -136,17 +135,17 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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AddressingMode::Absolute => {
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// Use [u8, ..2] from instruction as address
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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AddressingMode::AbsoluteX => {
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// Use [u8, ..2] from instruction as address, add X
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(x.into()))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]).wrapping_add(x.into()))
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}
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AddressingMode::AbsoluteY => {
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// Use [u8, ..2] from instruction as address, add Y
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()))
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}
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AddressingMode::Indirect => {
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// Use [u8, ..2] from instruction as an address. Interpret the
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@ -162,7 +161,7 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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// (Output: a 16-bit address)
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let start = slice[0].wrapping_add(x);
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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AddressingMode::IndirectIndexedY => {
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// Use [u8, ..1] from instruction
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@ -171,7 +170,7 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()))
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}
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};
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