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No commits in common. "536abef126d2379f21cf1d7272d30a38b8a776c7" and "0f1c01ce602229eb2677651e67e33f7e868454b0" have entirely different histories.
536abef126
...
0f1c01ce60
98
src/cpu.rs
98
src/cpu.rs
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@ -201,14 +201,6 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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)
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)
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}
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}
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AddressingMode::ZeroPageIndirect => {
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// Use [u8, ..1] from instruction
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// This is where the absolute (16-bit) target address is stored.
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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};
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};
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// Increment program counter
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// Increment program counter
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@ -282,16 +274,6 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.branch_if_not_equal(addr);
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self.branch_if_not_equal(addr);
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}
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}
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(Instruction::BIT, OpInput::UseImmediate(val)) => {
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::BIT, OpInput::UseAddress(addr)) => {
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(Instruction::BIT, OpInput::UseAddress(addr)) => {
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let a: u8 = self.registers.accumulator;
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let a: u8 = self.registers.accumulator;
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let m: u8 = self.memory.get_byte(addr);
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let m: u8 = self.memory.get_byte(addr);
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@ -344,18 +326,6 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.registers.status.or(Status::PS_DISABLE_INTERRUPTS);
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self.registers.status.or(Status::PS_DISABLE_INTERRUPTS);
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}
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}
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(Instruction::BRKcld, OpInput::UseImplied) => {
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for b in self.registers.program_counter.wrapping_sub(1).to_be_bytes() {
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self.push_on_stack(b);
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}
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self.push_on_stack(self.registers.status.bits());
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let pcl = self.memory.get_byte(0xfffe);
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let pch = self.memory.get_byte(0xffff);
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self.jump(((pch as u16) << 8) | pcl as u16);
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self.registers.status.or(Status::PS_DISABLE_INTERRUPTS);
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self.registers.status.and(!Status::PS_DECIMAL_MODE);
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}
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(Instruction::BVC, OpInput::UseRelative(rel)) => {
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(Instruction::BVC, OpInput::UseRelative(rel)) => {
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let addr = self.registers.program_counter.wrapping_add(rel);
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let addr = self.registers.program_counter.wrapping_add(rel);
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self.branch_if_overflow_clear(addr);
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self.branch_if_overflow_clear(addr);
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@ -501,47 +471,11 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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let val = self.registers.accumulator;
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let val = self.registers.accumulator;
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self.push_on_stack(val);
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self.push_on_stack(val);
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}
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}
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(Instruction::PHX, OpInput::UseImplied) => {
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// Push X
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self.push_on_stack(self.registers.index_x);
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}
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(Instruction::PHY, OpInput::UseImplied) => {
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// Push Y
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self.push_on_stack(self.registers.index_y);
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}
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(Instruction::PHP, OpInput::UseImplied) => {
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(Instruction::PHP, OpInput::UseImplied) => {
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// Push status
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// Push status
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let val = self.registers.status.bits() | 0x30;
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let val = self.registers.status.bits() | 0x30;
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self.push_on_stack(val);
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self.push_on_stack(val);
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}
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}
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(Instruction::PLX, OpInput::UseImplied) => {
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// Pull accumulator
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self.pull_from_stack();
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let val: u8 = self.fetch_from_stack();
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self.registers.index_x = val;
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self.registers.status.set_with_mask(
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Status::PS_ZERO | Status::PS_NEGATIVE,
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Status::new(StatusArgs {
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zero: val == 0,
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negative: self.registers.accumulator > 127,
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::PLY, OpInput::UseImplied) => {
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// Pull accumulator
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self.pull_from_stack();
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let val: u8 = self.fetch_from_stack();
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self.registers.index_y = val;
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self.registers.status.set_with_mask(
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Status::PS_ZERO | Status::PS_NEGATIVE,
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Status::new(StatusArgs {
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zero: val == 0,
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negative: self.registers.accumulator > 127,
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..StatusArgs::none()
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}),
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);
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}
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(Instruction::PLA, OpInput::UseImplied) => {
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(Instruction::PLA, OpInput::UseImplied) => {
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// Pull accumulator
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// Pull accumulator
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self.pull_from_stack();
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self.pull_from_stack();
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@ -658,38 +592,6 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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let val = self.registers.accumulator;
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let val = self.registers.accumulator;
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self.load_y_register(val);
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self.load_y_register(val);
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}
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}
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(Instruction::TRB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator set the corresponding bits in the operand
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let res = self.registers.accumulator | val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSB, OpInput::UseAddress(addr)) => {
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let val = self.memory.get_byte(addr);
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// The zero flag is set based on the result of the 'and'.
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self.registers.status.set_with_mask(
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Status::PS_ZERO,
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Status::new(StatusArgs {
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zero: 0 == (self.registers.accumulator & val),
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..StatusArgs::none()
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}),
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);
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// The 1's in the accumulator clear the corresponding bits in the operand
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let res = (self.registers.accumulator ^ 0xff) & val;
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self.memory.set_byte(addr, res);
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}
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(Instruction::TSX, OpInput::UseImplied) => {
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(Instruction::TSX, OpInput::UseImplied) => {
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let StackPointer(val) = self.registers.stack_pointer;
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let StackPointer(val) = self.registers.stack_pointer;
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self.load_x_register(val);
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self.load_x_register(val);
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@ -25,208 +25,88 @@
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// POSSIBILITY OF SUCH DAMAGE.
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// Abbreviations
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//
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// General
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//
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// M | `Memory location`
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//
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// Registers
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//
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// A | accumulator
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// X | general purpose register
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// Y | general purpose register
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// F | processor status flags, collectively
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// NV-BDIZC | processor status flags, individually
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// S | stack pointer
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// PC | program counter
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//
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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pub enum Instruction {
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pub enum Instruction {
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// ADd with Carry
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ADC, // ADd with Carry................ | NV ...ZC A = A + M + C
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ADC,
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ADCnd, // ADd with Carry................ | NV ...ZC A = A + M + C
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AND, // logical AND (bitwise)......... | N. ...Z. A = A && M
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// ADd with Carry. This one has now decimal mode.
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ASL, // Arithmetic Shift Left......... | N. ...ZC A = M << 1
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ADCnd,
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BCC, // Branch if Carry Clear......... | .. ..... PC = !C
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BCS, // Branch if Carry Set........... | .. ..... PC = C
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// logical AND (bitwise)
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BEQ, // Branch if Equal (to zero?).... | .. ..... PC = Z
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AND,
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BIT, // BIT test...................... | NV ...Z. = A & M
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BMI, // Branch if Minus............... | .. ..... PC = N
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// Arithmetic Shift Left
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BNE, // Branch if Not Equal........... | .. ..... PC = !Z
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ASL,
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BPL, // Branch if Positive............ | .. ..... PC = Z
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BRA, // Unconditional BRAnch.......... | .. B.... S PC =
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// Branch if Carry Clear
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BRK, // BReaK......................... | .. B.... S PC =
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||||||
BCC,
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BVC, // Branch if oVerflow Clear...... | .. ..... PC = !V
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BVS, // Branch if oVerflow Set........ | .. ..... PC = V
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// Branch if Carry Set
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CLC, // CLear Carry flag.............. | .. ....C = 0
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BCS,
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CLD, // Clear Decimal Mode............ | .. .D... = 0
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||||||
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CLI, // Clear Interrupt Disable....... | .. ..I.. = 0
|
||||||
// Branch if Equal (to zero?)
|
CLV, // Clear oVerflow flag........... | .V ..... = 0
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BEQ,
|
CMP, // Compare....................... | N. ...ZC = A - M
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CPX, // Compare X register............ | N. ...ZC = X - M
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// BIT test
|
CPY, // Compare Y register............ | N. ...ZC = Y - M
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BIT,
|
DEC, // DECrement memory.............. | N. ...Z. M = M - 1
|
||||||
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DEX, // DEcrement X register.......... | N. ...Z. X = X - 1
|
||||||
// Branch if Minus
|
DEY, // DEcrement Y register.......... | N. ...Z. Y = Y - 1
|
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BMI,
|
EOR, // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
|
||||||
|
INC, // INCrement memory.............. | N. ...Z. M = M + 1
|
||||||
// Branch if Not Equal
|
INX, // INcrement X register.......... | N. ...Z. X = X + 1
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||||||
BNE,
|
INY, // INcrement Y register.......... | N. ...Z. Y = Y + 1
|
||||||
|
JMP, // JuMP.......................... | .. ..... S PC =
|
||||||
// Branch if Positive
|
JSR, // Jump to SubRoutine............ | .. ..... S PC =
|
||||||
BPL,
|
LDA, // LoaD Accumulator.............. | N. ...Z. A = M
|
||||||
|
LDX, // LoaD X register............... | N. ...Z. X = M
|
||||||
// Unconditional BRAnch
|
LDY, // LoaD Y register............... | N. ...Z. Y = M
|
||||||
BRA,
|
LSR, // Logical Shift Right........... | N. ...ZC A = A/2
|
||||||
|
// or N. ...ZC M = M/2
|
||||||
// BReaK
|
NOP, // No OPeration.................. | .. ..... =
|
||||||
BRK,
|
ORA, // inclusive OR (bitwise)........ | N. ...Z. A = A | M
|
||||||
|
PHA, // PusH Accumulator.............. | .. ..... S M = A
|
||||||
// BReaK, clearing decimal flag
|
PHP, // PusH Processor status......... | .. ..... S M = F
|
||||||
BRKcld,
|
PLA, // PuLl Accumulator.............. | N. ...Z. A S = M (stack)
|
||||||
|
PLP, // PuLl Processor status......... | NV BDIZC S = M (stack)
|
||||||
// Branch if oVerflow Clear
|
ROL, // ROtate Left................... | N. ...ZC A = C A rotated
|
||||||
BVC,
|
// or N. ...ZC M = C M rotated
|
||||||
|
ROR, // ROtate Right.................. | N. ...ZC A = C A rotated
|
||||||
// Branch if oVerflow Set
|
// or N. ...ZC M = C M rotated
|
||||||
BVS,
|
RTI, // ReTurn from Interrupt......... | NV BDIZC PC = M (stack)
|
||||||
|
RTS, // ReTurn from Subroutine........ | .. ..... PC = M (stack)
|
||||||
// CLear Carry flag
|
SBC, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
|
||||||
CLC,
|
SBCnd, // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
|
||||||
|
SEC, // SEt Carry flag................ | .. ....C = 1
|
||||||
// Clear Decimal Mode
|
SED, // SEt Decimal flag.............. | .. .D... = 1
|
||||||
CLD,
|
SEI, // SEt Interrupt disable......... | .. ..I.. = 1
|
||||||
|
STA, // STore Accumulator............. | .. ..... M = A
|
||||||
// Clear Interrupt Disable
|
STX, // STore X register.............. | .. ..... M = X
|
||||||
CLI,
|
STY, // STore Y register.............. | .. ..... M = Y
|
||||||
|
STZ, // STore Zero.................... | .. ..... M = Y
|
||||||
// Clear oVerflow flag
|
TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
|
||||||
CLV,
|
TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
|
||||||
|
TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
|
||||||
// Compare
|
TXA, // Transfer X to Accumulator..... | N. ...Z. A = X
|
||||||
CMP,
|
TXS, // Transfer X to Stack pointer... | .. ..... S = X
|
||||||
|
TYA, // Transfer Y to Accumulator..... | N. ...Z. A = Y
|
||||||
// Compare X register
|
|
||||||
CPX,
|
|
||||||
|
|
||||||
// Compare Y register
|
|
||||||
CPY,
|
|
||||||
|
|
||||||
// DECrement memory
|
|
||||||
DEC,
|
|
||||||
|
|
||||||
// DEcrement X register
|
|
||||||
DEX,
|
|
||||||
|
|
||||||
// DEcrement Y register
|
|
||||||
DEY,
|
|
||||||
|
|
||||||
// Exclusive OR (bitwise)
|
|
||||||
EOR,
|
|
||||||
|
|
||||||
// INCrement memory
|
|
||||||
INC,
|
|
||||||
|
|
||||||
// INcrement X register
|
|
||||||
INX,
|
|
||||||
|
|
||||||
// INcrement Y register
|
|
||||||
INY,
|
|
||||||
|
|
||||||
// JuMP
|
|
||||||
JMP,
|
|
||||||
|
|
||||||
// Jump to SubRoutine
|
|
||||||
JSR,
|
|
||||||
|
|
||||||
// LoaD Accumulator
|
|
||||||
LDA,
|
|
||||||
|
|
||||||
// LoaD X register
|
|
||||||
LDX,
|
|
||||||
|
|
||||||
// LoaD Y register
|
|
||||||
LDY,
|
|
||||||
|
|
||||||
// Logical Shift Right
|
|
||||||
LSR,
|
|
||||||
|
|
||||||
// No OPeration
|
|
||||||
NOP,
|
|
||||||
|
|
||||||
// inclusive OR (bitwise)
|
|
||||||
ORA,
|
|
||||||
|
|
||||||
// PusH Accumulator
|
|
||||||
PHA,
|
|
||||||
|
|
||||||
// PusH X
|
|
||||||
PHX,
|
|
||||||
|
|
||||||
// PusH Y
|
|
||||||
PHY,
|
|
||||||
|
|
||||||
// PusH Processor status
|
|
||||||
PHP,
|
|
||||||
|
|
||||||
// PuLl Accumulator
|
|
||||||
PLA,
|
|
||||||
|
|
||||||
// PuLl X
|
|
||||||
PLX,
|
|
||||||
|
|
||||||
// PuLl Y
|
|
||||||
PLY,
|
|
||||||
|
|
||||||
// PuLl Processor status
|
|
||||||
PLP,
|
|
||||||
|
|
||||||
// ROtate Left
|
|
||||||
ROL,
|
|
||||||
|
|
||||||
// ROtate Right
|
|
||||||
ROR,
|
|
||||||
|
|
||||||
// ReTurn from Interrupt
|
|
||||||
RTI,
|
|
||||||
|
|
||||||
// ReTurn from Subroutine
|
|
||||||
RTS,
|
|
||||||
|
|
||||||
// SuBtract with Carry
|
|
||||||
SBC,
|
|
||||||
|
|
||||||
// SuBtract with Carry. This one has now decimal mode.
|
|
||||||
SBCnd,
|
|
||||||
|
|
||||||
// SEt Carry flag
|
|
||||||
SEC,
|
|
||||||
|
|
||||||
// SEt Decimal flag
|
|
||||||
SED,
|
|
||||||
|
|
||||||
// SEt Interrupt disable
|
|
||||||
SEI,
|
|
||||||
|
|
||||||
// STore Accumulator
|
|
||||||
STA,
|
|
||||||
|
|
||||||
// STore X register
|
|
||||||
STX,
|
|
||||||
|
|
||||||
// STore Y register
|
|
||||||
STY,
|
|
||||||
|
|
||||||
// STore Zero
|
|
||||||
STZ,
|
|
||||||
|
|
||||||
// Transfer Accumulator to X
|
|
||||||
TAX,
|
|
||||||
|
|
||||||
// Transfer Accumulator to Y
|
|
||||||
TAY,
|
|
||||||
|
|
||||||
// Test and Reset Bits
|
|
||||||
TRB,
|
|
||||||
|
|
||||||
// Test and Set Bits
|
|
||||||
TSB,
|
|
||||||
|
|
||||||
// Transfer Stack pointer to X
|
|
||||||
TSX,
|
|
||||||
|
|
||||||
// Transfer X to Accumulator
|
|
||||||
TXA,
|
|
||||||
|
|
||||||
// Transfer X to Stack pointer
|
|
||||||
TXS,
|
|
||||||
|
|
||||||
// Transfer Y to Accumulator
|
|
||||||
TYA,
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Copy, Clone)]
|
#[derive(Copy, Clone)]
|
||||||
|
@ -280,9 +160,6 @@ pub enum AddressingMode {
|
||||||
|
|
||||||
// load from (address stored at constant zero page address) plus Y register, e. g. `lda ($10),Y`.
|
// load from (address stored at constant zero page address) plus Y register, e. g. `lda ($10),Y`.
|
||||||
IndirectIndexedY,
|
IndirectIndexedY,
|
||||||
|
|
||||||
// Address stored at constant zero page address
|
|
||||||
ZeroPageIndirect,
|
|
||||||
}
|
}
|
||||||
|
|
||||||
impl AddressingMode {
|
impl AddressingMode {
|
||||||
|
@ -302,7 +179,6 @@ impl AddressingMode {
|
||||||
AddressingMode::BuggyIndirect => 2,
|
AddressingMode::BuggyIndirect => 2,
|
||||||
AddressingMode::IndexedIndirectX => 1,
|
AddressingMode::IndexedIndirectX => 1,
|
||||||
AddressingMode::IndirectIndexedY => 1,
|
AddressingMode::IndirectIndexedY => 1,
|
||||||
AddressingMode::ZeroPageIndirect => 1,
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -615,7 +491,6 @@ impl crate::Variant for Cmos6502 {
|
||||||
fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
|
fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
|
||||||
// TODO: We obviously need to add the other CMOS instructions here.
|
// TODO: We obviously need to add the other CMOS instructions here.
|
||||||
match opcode {
|
match opcode {
|
||||||
0x00 => Some((Instruction::BRKcld, AddressingMode::Implied)),
|
|
||||||
0x1a => Some((Instruction::INC, AddressingMode::Accumulator)),
|
0x1a => Some((Instruction::INC, AddressingMode::Accumulator)),
|
||||||
0x3a => Some((Instruction::DEC, AddressingMode::Accumulator)),
|
0x3a => Some((Instruction::DEC, AddressingMode::Accumulator)),
|
||||||
0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
|
0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
|
||||||
|
@ -624,23 +499,6 @@ impl crate::Variant for Cmos6502 {
|
||||||
0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)),
|
0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)),
|
||||||
0x9c => Some((Instruction::STZ, AddressingMode::Absolute)),
|
0x9c => Some((Instruction::STZ, AddressingMode::Absolute)),
|
||||||
0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)),
|
0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)),
|
||||||
0x7a => Some((Instruction::PLY, AddressingMode::Implied)),
|
|
||||||
0xfa => Some((Instruction::PLX, AddressingMode::Implied)),
|
|
||||||
0x5a => Some((Instruction::PHY, AddressingMode::Implied)),
|
|
||||||
0xda => Some((Instruction::PHX, AddressingMode::Implied)),
|
|
||||||
0x04 => Some((Instruction::TSB, AddressingMode::ZeroPage)),
|
|
||||||
0x14 => Some((Instruction::TRB, AddressingMode::ZeroPage)),
|
|
||||||
0x0c => Some((Instruction::TSB, AddressingMode::Absolute)),
|
|
||||||
0x1c => Some((Instruction::TRB, AddressingMode::Absolute)),
|
|
||||||
0x12 => Some((Instruction::ORA, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0x32 => Some((Instruction::AND, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0x52 => Some((Instruction::EOR, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0x72 => Some((Instruction::ADC, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0x92 => Some((Instruction::STA, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0xb2 => Some((Instruction::LDA, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0xd2 => Some((Instruction::CMP, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0xf2 => Some((Instruction::SBC, AddressingMode::ZeroPageIndirect)),
|
|
||||||
0x89 => Some((Instruction::BIT, AddressingMode::Immediate)),
|
|
||||||
_ => Nmos6502::decode(opcode),
|
_ => Nmos6502::decode(opcode),
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue
Block a user