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54196929d8
Author | SHA1 | Date |
---|---|---|
omarandlorraine | 54196929d8 | |
Sam M W | 0f1c01ce60 | |
Sam M W | 2c26ebb00a | |
Sam M W | df51b077e7 | |
Sam M W | 309ad50374 | |
Sam M W | 4847744518 | |
Matthias Endler | 11d9540729 | |
Sam M W | bf06ad8924 | |
Sam M W | 54dd0cd536 | |
Sam M W | 2444ef52d1 | |
Sam M W | ad622bc930 | |
Sam M W | 97d6b3fd89 | |
Sam M W | da30c8c67d |
62
src/cpu.rs
62
src/cpu.rs
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@ -31,10 +31,8 @@ use crate::Variant;
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use crate::registers::{Registers, StackPointer, Status, StatusArgs};
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fn arr_to_addr(arr: &[u8]) -> u16 {
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debug_assert!(arr.len() == 2);
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u16::from(arr[0]) + (u16::from(arr[1]) << 8usize)
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fn address_from_bytes(lo: u8, hi: u8) -> u16 {
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u16::from(lo) + (u16::from(hi) << 8usize)
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}
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#[derive(Clone)]
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@ -136,24 +134,52 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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AddressingMode::Absolute => {
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// Use [u8, ..2] from instruction as address
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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AddressingMode::AbsoluteX => {
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// Use [u8, ..2] from instruction as address, add X
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(x.into()))
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OpInput::UseAddress(
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address_from_bytes(slice[0], slice[1]).wrapping_add(x.into()),
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)
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}
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AddressingMode::AbsoluteY => {
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// Use [u8, ..2] from instruction as address, add Y
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// (Output: a 16-bit address)
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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OpInput::UseAddress(
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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)
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}
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AddressingMode::Indirect => {
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// Use [u8, ..2] from instruction as an address. Interpret the
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// two bytes starting at that address as an address.
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// (Output: a 16-bit address)
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let slice = read_address(memory, arr_to_addr(&slice));
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OpInput::UseAddress(arr_to_addr(&slice))
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// TODO: If the pointer ends in 0xff, then incrementing it would propagate
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// the carry to the high byte of the pointer. This incurs a cost of one
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// machine cycle on the real 65C02, which is not implemented here.
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let slice = read_address(memory, address_from_bytes(slice[0], slice[1]));
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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AddressingMode::BuggyIndirect => {
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// Use [u8, ..2] from instruction as an address. Interpret the
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// two bytes starting at that address as an address.
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// (Output: a 16-bit address)
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let pointer = address_from_bytes(slice[0], slice[1]);
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let low_byte_of_target = memory.get_byte(pointer);
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let low_byte_of_incremented_pointer =
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pointer.to_le_bytes()[0].wrapping_add(1);
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let incremented_pointer = u16::from_le_bytes([
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low_byte_of_incremented_pointer,
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pointer.to_le_bytes()[1],
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]);
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let high_byte_of_target = memory.get_byte(incremented_pointer);
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OpInput::UseAddress(address_from_bytes(
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low_byte_of_target,
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high_byte_of_target,
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))
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}
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AddressingMode::IndexedIndirectX => {
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// Use [u8, ..1] from instruction
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@ -162,7 +188,7 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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// (Output: a 16-bit address)
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let start = slice[0].wrapping_add(x);
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice))
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OpInput::UseAddress(address_from_bytes(slice[0], slice[1]))
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}
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AddressingMode::IndirectIndexedY => {
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// Use [u8, ..1] from instruction
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@ -171,7 +197,9 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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// (Output: a 16-bit address)
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let start = slice[0];
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let slice = read_address(memory, u16::from(start));
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OpInput::UseAddress(arr_to_addr(&slice).wrapping_add(y.into()))
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OpInput::UseAddress(
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address_from_bytes(slice[0], slice[1]).wrapping_add(y.into()),
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)
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}
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};
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@ -282,6 +310,11 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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self.branch_if_positive(addr);
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}
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(Instruction::BRA, OpInput::UseRelative(rel)) => {
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let addr = self.registers.program_counter.wrapping_add(rel);
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self.branch(addr);
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}
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(Instruction::BRK, OpInput::UseImplied) => {
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for b in self.registers.program_counter.wrapping_sub(1).to_be_bytes() {
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self.push_on_stack(b);
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@ -547,6 +580,9 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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(Instruction::STY, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, self.registers.index_y);
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}
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(Instruction::STZ, OpInput::UseAddress(addr)) => {
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self.memory.set_byte(addr, 0);
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}
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(Instruction::TAX, OpInput::UseImplied) => {
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let val = self.registers.accumulator;
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@ -979,6 +1015,10 @@ impl<M: Bus, V: Variant> CPU<M, V> {
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}
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}
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fn branch(&mut self, addr: u16) {
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self.registers.program_counter = addr;
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}
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fn branch_if_positive(&mut self, addr: u16) {
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if !self.registers.status.contains(Status::PS_NEGATIVE) {
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self.registers.program_counter = addr;
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@ -55,6 +55,7 @@ pub enum Instruction {
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BMI, // Branch if Minus............... | .. ..... PC = N
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BNE, // Branch if Not Equal........... | .. ..... PC = !Z
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BPL, // Branch if Positive............ | .. ..... PC = Z
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BRA, // Unconditional BRAnch.......... | .. B.... S PC =
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BRK, // BReaK......................... | .. B.... S PC =
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BVC, // Branch if oVerflow Clear...... | .. ..... PC = !V
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BVS, // Branch if oVerflow Set........ | .. ..... PC = V
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@ -99,6 +100,7 @@ pub enum Instruction {
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STA, // STore Accumulator............. | .. ..... M = A
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STX, // STore X register.............. | .. ..... M = X
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STY, // STore Y register.............. | .. ..... M = Y
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STZ, // STore Zero.................... | .. ..... M = Y
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TAX, // Transfer Accumulator to X..... | N. ...Z. X = A
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TAY, // Transfer Accumulator to Y..... | N. ...Z. Y = A
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TSX, // Transfer Stack pointer to X... | N. ...Z. X = S
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@ -117,21 +119,47 @@ pub enum OpInput {
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#[derive(Copy, Clone)]
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pub enum AddressingMode {
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Accumulator, // 1 LSR A work directly on accumulator
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Implied, // 1 BRK
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Immediate, // 2 LDA #10 8-bit constant in instruction
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ZeroPage, // 2 LDA $00 zero-page address
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ZeroPageX, // 2 LDA $80,X address is X register + 8-bit constant
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ZeroPageY, // 2 LDX $10,Y address is Y register + 8-bit constant
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Relative, // 2 BNE LABEL branch target as signed relative offset
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Absolute, // 3 JMP $1000 full 16-bit address
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AbsoluteX, // 3 STA $1000,X full 16-bit address plus X register
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AbsoluteY, // 3 STA $1000,Y full 16-bit address plus Y register
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Indirect, // 3 JMP ($1000) jump to address stored at address
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IndexedIndirectX, // 2 LDA ($10,X) load from address stored at (constant
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// zero page address plus X register)
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IndirectIndexedY, // 2 LDA ($10),Y load from (address stored at constant
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// zero page address) plus Y register
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// work directly on accumulator, e. g. `lsr a`.
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Accumulator,
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// BRK
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Implied,
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// 8-bit constant in instruction, e. g. `lda #10`.
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Immediate,
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// zero-page address, e. g. `lda $00`.
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ZeroPage,
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// address is X register + 8-bit constant, e. g. `lda $80,x`.
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ZeroPageX,
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// address is Y register + 8-bit constant, e. g. `ldx $10,y`.
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ZeroPageY,
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// branch target as signed relative offset, e. g. `bne label`.
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Relative,
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// full 16-bit address, e. g. `jmp $1000`.
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Absolute,
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// full 16-bit address plus X register, e. g. `sta $1000,X`.
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AbsoluteX,
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// full 16-bit address plus Y register, e. g. `sta $1000,Y`.
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AbsoluteY,
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// jump to address stored at address, with the page-crossing bug found in NMOS chips, e. g. `jmp ($1000)`.
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BuggyIndirect,
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// jump to address stored at address, e. g. `jmp ($1000)`.
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Indirect,
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// load from address stored at (constant zero page address plus X register), e. g. `lda ($10,X)`.
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IndexedIndirectX,
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// load from (address stored at constant zero page address) plus Y register, e. g. `lda ($10),Y`.
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IndirectIndexedY,
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}
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impl AddressingMode {
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@ -148,6 +176,7 @@ impl AddressingMode {
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AddressingMode::AbsoluteX => 2,
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AddressingMode::AbsoluteY => 2,
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AddressingMode::Indirect => 2,
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AddressingMode::BuggyIndirect => 2,
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AddressingMode::IndexedIndirectX => 1,
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AddressingMode::IndirectIndexedY => 1,
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}
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@ -270,7 +299,7 @@ impl crate::Variant for Nmos6502 {
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0x69 => Some((Instruction::ADC, AddressingMode::Immediate)),
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0x6a => Some((Instruction::ROR, AddressingMode::Accumulator)),
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0x6b => None,
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0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
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0x6c => Some((Instruction::JMP, AddressingMode::BuggyIndirect)),
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0x6d => Some((Instruction::ADC, AddressingMode::Absolute)),
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0x6e => Some((Instruction::ROR, AddressingMode::Absolute)),
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0x6f => None,
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@ -428,24 +457,15 @@ pub struct Ricoh2a03;
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impl crate::Variant for Ricoh2a03 {
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fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
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match opcode {
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0x61 => Some((Instruction::ADCnd, AddressingMode::IndexedIndirectX)),
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0x65 => Some((Instruction::ADCnd, AddressingMode::ZeroPage)),
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0x69 => Some((Instruction::ADCnd, AddressingMode::Immediate)),
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0x6d => Some((Instruction::ADCnd, AddressingMode::Absolute)),
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0x71 => Some((Instruction::ADCnd, AddressingMode::IndirectIndexedY)),
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0x75 => Some((Instruction::ADCnd, AddressingMode::ZeroPageX)),
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0x79 => Some((Instruction::ADCnd, AddressingMode::AbsoluteY)),
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0x7d => Some((Instruction::ADCnd, AddressingMode::AbsoluteX)),
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0xe1 => Some((Instruction::SBCnd, AddressingMode::IndexedIndirectX)),
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0xe5 => Some((Instruction::SBCnd, AddressingMode::ZeroPage)),
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0xe9 => Some((Instruction::SBCnd, AddressingMode::Immediate)),
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0xed => Some((Instruction::SBCnd, AddressingMode::Absolute)),
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0xf1 => Some((Instruction::SBCnd, AddressingMode::IndirectIndexedY)),
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0xf5 => Some((Instruction::SBCnd, AddressingMode::ZeroPageX)),
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0xf9 => Some((Instruction::SBCnd, AddressingMode::AbsoluteY)),
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0xfd => Some((Instruction::SBCnd, AddressingMode::AbsoluteX)),
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_ => Nmos6502::decode(opcode),
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// It's the same as on NMOS, but doesn't support decimal mode.
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match Nmos6502::decode(opcode) {
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Some((Instruction::ADC, addressing_mode)) => {
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Some((Instruction::ADCnd, addressing_mode))
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}
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Some((Instruction::SBC, addressing_mode)) => {
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Some((Instruction::SBCnd, addressing_mode))
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}
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something_else => something_else,
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}
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}
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}
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@ -456,12 +476,29 @@ pub struct RevisionA;
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impl crate::Variant for RevisionA {
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fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
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// It's the same as on NMOS, but has no ROR instruction.
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match Nmos6502::decode(opcode) {
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Some((Instruction::ROR, _)) => None,
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something_else => something_else,
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}
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}
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}
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/// Emulates the 65C02, which has a few bugfixes, and another addressing mode
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pub struct Cmos6502;
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impl crate::Variant for Cmos6502 {
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fn decode(opcode: u8) -> Option<(Instruction, AddressingMode)> {
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// TODO: We obviously need to add the other CMOS instructions here.
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match opcode {
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0x66 => None,
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0x6a => None,
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0x6e => None,
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0x76 => None,
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0x7e => None,
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0x1a => Some((Instruction::INC, AddressingMode::Accumulator)),
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0x3a => Some((Instruction::DEC, AddressingMode::Accumulator)),
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0x6c => Some((Instruction::JMP, AddressingMode::Indirect)),
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0x80 => Some((Instruction::BRA, AddressingMode::Relative)),
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0x64 => Some((Instruction::STZ, AddressingMode::ZeroPage)),
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0x74 => Some((Instruction::STZ, AddressingMode::ZeroPageX)),
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0x9c => Some((Instruction::STZ, AddressingMode::Absolute)),
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0x9e => Some((Instruction::STZ, AddressingMode::AbsoluteX)),
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_ => Nmos6502::decode(opcode),
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}
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}
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