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112 lines
6.2 KiB
Rust
112 lines
6.2 KiB
Rust
// Copyright (C) 2014 The 6502-rs Developers
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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// 3. Neither the names of the copyright holders nor the names of any
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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// Abbreviations
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//
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// General
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//
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// M | `Memory location`
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//
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// Registers
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//
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// A | accumulator
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// X | general purpose register
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// Y | general purpose register
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// F | processor status flags, collectively
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// NV-BDIZC | processor status flags, individually
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// S | stack pointer
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// PC | program counter
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//
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#[deriving(Show, PartialEq, Eq)]
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pub enum Instruction
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// i/o vars should be listed as follows:
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// NV BDIZC A X Y S PC M
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//
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// | outputs | inputs
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{ ADC // ADd with Carry................ | NV ...ZC A = A + M + C
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, AND // logical AND (bitwise)......... | N. ...Z. A = A && M
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, ASL // Arithmetic Shift Left......... | N. ...ZC A = M << 1
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, BCC // Branch if Carry Clear......... | .. ..... PC = !C
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, BCS // Branch if Carry Set........... | .. ..... PC = C
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, BEQ // Branch if Equal (to zero?).... | .. ..... PC = Z
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, BIT // BIT test...................... | NV ...Z. = A & M
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, BMI // Branch if Minus............... | .. ..... PC = N
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, BNE // Branch if Not Equal........... | .. ..... PC = !Z
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, BPL // Branch if Positive............ | .. ..... PC = Z
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, BRK // BReaK......................... | .. B.... S PC =
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, BVC // Branch if oVerflow Clear...... | .. ..... PC = !V
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, BVS // Branch if oVerflow Set........ | .. ..... PC = V
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, CLC // CLear Carry flag.............. | .. ....C = 0
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, CLD // Clear Decimal Mode............ | .. .D... = 0
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, CLI // Clear Interrupt Disable....... | .. ..I.. = 0
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, CLV // Clear oVerflow flag........... | .V ..... = 0
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, CMP // Compare....................... | N. ...ZC = A - M
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, CPX // Compare X register............ | N. ...ZC = X - M
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, CPY // Compare Y register............ | N. ...ZC = Y - M
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, DEC // DECrement memory.............. | N. ...Z. M = M - 1
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, DEX // DEcrement X register.......... | N. ...Z. X = X - 1
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, DEY // DEcrement Y register.......... | N. ...Z. Y = Y - 1
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, EOR // Exclusive OR (bitwise)........ | N. ...Z. A = A ^ M
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, INC // INCrement memory.............. | N. ...Z. M = M + 1
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, INX // INcrement X register.......... | N. ...Z. X = X + 1
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, INY // INcrement Y register.......... | N. ...Z. Y = Y + 1
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, JMP // JuMP.......................... | .. ..... S PC =
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, JSR // Jump to SubRoutine............ | .. ..... S PC =
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, LDA // LoaD Accumulator.............. | N. ...Z. A = M
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, LDX // LoaD X register............... | N. ...Z. X = M
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, LDY // LoaD Y register............... | N. ...Z. Y = M
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, LSR // Logical Shift Right........... | N. ...ZC A = A/2
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// or N. ...ZC M = M/2
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, NOP // No OPeration.................. | .. ..... =
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, ORA // inclusive OR (bitwise)........ | N. ...Z. A = A | M
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, PHA // PusH Accumulator.............. | .. ..... S M = A
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, PHP // PusH Processor status......... | .. ..... S M = F
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, PLA // PuLl Accumulator.............. | N. ...Z. A S = M (stack)
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, PLP // PuLl Processor status......... | NV BDIZC S = M (stack)
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, ROL // ROtate Left................... | N. ...ZC A = C A rotated
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// or N. ...ZC M = C M rotated
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, ROR // ROtate Right.................. | N. ...ZC A = C A rotated
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// or N. ...ZC M = C M rotated
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, RTI // ReTurn from Interrupt......... | NV BDIZC PC = M (stack)
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, RTS // ReTurn from Subroutine........ | .. ..... PC = M (stack)
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, SBC // SuBtract with Carry........... | NV ...ZC A = A-M-(1-C)
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, SEC // SEt Carry flag................ | .. ....C = 1
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, SED // SEt Decimal flag.............. | .. .D... = 1
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, SEI // SEt Interrupt disable......... | .. ..I.. = 1
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, STA // STore Accumulator............. | .. ..... M = A
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, STX // STore X register.............. | .. ..... M = X
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, STY // STore Y register.............. | .. ..... M = Y
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, TAX // Transfer Accumulator to X..... | N. ...Z. X = A
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, TAY // Transfer Accumulator to Y..... | N. ...Z. Y = A
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, TSX // Transfer Stack pointer to X... | N. ...Z. X = S
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, TXA // Transfer X to Accumulator..... | N. ...Z. A = X
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, TXS // Transfer X to Stack pointer... | .. ..... S = X
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, TYA // Transfer Y to Accumulator..... | N. ...Z. A = Y
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}
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