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https://github.com/mgcaret/of816.git
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246 lines
5.3 KiB
ArmAsm
246 lines
5.3 KiB
ArmAsm
; Platform support library for GoSXB
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cpu_clk = 8000000
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.enum ACIA
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RXD
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SR
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CMD
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CTL
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TXD = RXD
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.endenum
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ACIA1 = $7F80
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.enum PIA
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PIA
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CRA
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PIB
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CRB
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DDRA = PIA
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DDRB = PIB
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.endenum
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PIA1 = $7FA0
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.enum VIA
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ORB
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ORA
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DDRB
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DDRA
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T1C_L
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T1C_H
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T1L_L
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T1L_H
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T2C_L
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T2C_H
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SR
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ACR
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PCR
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IFR
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IER
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ORA2
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IRB = ORB
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IRA = ORA
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.endenum
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VIA1 = $7FC0
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VIA2 = $7FE0
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.proc _system_interface
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;wdm 3
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phx
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asl
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tax
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jmp (.loword(table),x)
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table: .addr _sf_pre_init
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.addr _sf_post_init
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.addr _sf_emit
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.addr _sf_keyq
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.addr _sf_key
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.addr _sf_fcode
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.addr _sf_reset_all
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.endproc
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.export _system_interface
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.proc _sf_success
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lda #$0000
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tay
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clc
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rtl
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.endproc
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.proc _sf_fail
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ldy #.loword(-21)
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lda #.hiword(-21)
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sec
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rtl
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.endproc
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.proc _sf_pre_init
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.if 1
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plx
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jmp _sf_success ; assume WDC monitor already did it
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.else
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; set up TIDE interface, the same way WDC does it
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php
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sep #SHORT_A|SHORT_I
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.a8
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.i8
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lda #$00
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sta VIA2+VIA::ACR
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lda #$00
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sta VIA2+VIA::PCR
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lda #%00011000 ; b3 = TUSB_RDB; b4 = ???
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sta VIA2+VIA::ORB
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lda #%00011100 ; set PB2, PB3, PB4 as outputs
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sta VIA2+VIA::DDRB
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lda #$00
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sta VIA2+VIA::DDRA
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lda VIA2+VIA::IRB
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pha
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and #%11101111 ; b4 = ???
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sta VIA2+VIA::ORB
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ldx #$5d
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jsr wait
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pla
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sta VIA2+VIA::ORB
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lda #%00100000 ; b5 = TUSB_PWRENB
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: bit VIA2+VIA::IRB ; wait for USB configuration
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bne :-
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plp
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plx
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jmp _sf_success
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wait: phx ; note 8-bit mode!
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ldx #$00
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: dex
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bne :-
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plx
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dex
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bne wait
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rts
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.a16
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.i16
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.endif
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.endproc
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.proc _sf_post_init
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plx
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jmp _sf_success
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.endproc
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.proc _sf_emit
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plx
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jsr _popay
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phx
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php
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sep #SHORT_A|SHORT_I
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.a8
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.i8
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lda #$00 ; ensure VIA2 DDR A is set up for input
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sta f:VIA2+VIA::DDRA
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tya
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sta f:VIA2+VIA::ORA ; set output byte to be sent
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: lda f:VIA2+VIA::IRB ; wait for FT245RL to be ready to transmit
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bit #%00000001 ; b0 = TUSB_TXEB
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bne :-
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lda f:VIA2+VIA::IRB
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and #%11111011 ; b2 = TUSB_WR
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tax
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ora #%00000100
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sta f:VIA2+VIA::ORB ; ensure FT245RL WR high
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lda #$ff ; set up DDR A for output
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sta f:VIA2+VIA::DDRA ; to present byte to send
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nop ; delay a few cycles
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txa
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sta f:VIA2+VIA::ORB ; strobe FT245RL WR low
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lda VIA2+VIA::IRA ; get output byte back (we don't really need it)
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xba
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lda #$00
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sta f:VIA2+VIA::DDRA ; switch DDR A back to input
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xba
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plp
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.a16
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.i16
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plx
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jmp _sf_success
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.endproc
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.proc _sf_keyq
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lda #$00
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tay ; anticipate false
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php
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sep #SHORT_A
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.a8
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sta f:VIA2+VIA::DDRA
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lda f:VIA2+VIA::IRB
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bit #%00000010
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bne :+
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dey ; from $0000 to $FFFF
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: plp
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.a16
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tya
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plx
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jsr _pushay
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jmp _sf_success
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.endproc
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.proc _sf_key
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php
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tay
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sep #SHORT_A|SHORT_I
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.a8
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.i8
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lda #$00
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sta f:VIA2+VIA::DDRA ; Ensure VIA2 DDR A is set up for input
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: lda f:VIA2+VIA::IRB ; wait for FT245RL to have data & be ready
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bit #%00000010 ; b1 = TUSB_RXFB
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bne :-
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lda f:VIA2+VIA::IRB
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ora #%00001000 ;b3 = TUSB_RDB
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tax
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and #%11110111
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sta f:VIA2+VIA::ORB ; strobe FT245RL RD# low
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nop ;delay some cycles
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nop
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nop
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nop
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lda f:VIA2+VIA::IRA ; receive byte
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tay
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txa
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sta f:VIA2+VIA::ORB ; strobe FT245RL RD# high
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plp
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.a16
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.i16
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lda #$0000
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plx
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jsr _pushay
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jmp _sf_success
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.endproc
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.proc _sf_fcode
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.if include_fcode
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ldy #.loword(list)
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lda #.hiword(list)
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.else
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lda #$0000
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tay
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.endif
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plx
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jsr _pushay
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jmp _sf_success
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.if include_fcode
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list:
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.dword 0
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.endif
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.endproc
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; SXB really can't do this when ROM is banked out. Maybe restart Forth instead?
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.proc _sf_reset_all
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plx
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jmp _sf_fail
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.endproc
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