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Improve input mode handling

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* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
This commit is contained in:
marqs 2017-02-07 23:04:30 +02:00
parent 3b19b2843c
commit 6e043ef577
17 changed files with 1264 additions and 1145 deletions
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4
ossc.cof
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@ -13,11 +13,11 @@
<sof_filename>output_files/ossc.sof</sof_filename>
</bit0>
</sof_data>
<version>9</version>
<version>10</version>
<create_cvp_file>0</create_cvp_file>
<create_hps_iocsr>0</create_hps_iocsr>
<auto_create_rpd>0</auto_create_rpd>
<create_fif_file>0</create_fif_file>
<rpd_little_endian>1</rpd_little_endian>
<options>
<map_file>1</map_file>
</options>

2
ossc.qsf
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@ -232,4 +232,6 @@ set_global_assignment -name QIP_FILE rtl/pll_2x.qip
set_global_assignment -name QIP_FILE rtl/pll_3x.qip
set_global_assignment -name CDF_FILE output_files/Chain1.cdf
set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
ossc.sdc
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@ -10,10 +10,10 @@ set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
### Scanconverter clock constraints ###
create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
create_clock -period 13.5MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L2 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L3 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L4 [get_ports PCLK_in] -add
create_clock -period 16MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
create_clock -period 27MHz -name pclk_sdtv_L5 [get_ports PCLK_in] -add
#derive_pll_clocks
create_generated_clock -master_clock pclk_sdtv_L2 -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}

10
rtl/pll_2x.v
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@ -117,7 +117,7 @@ module pll_2x (
altpll_component.clk1_multiply_by = 5,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 74074,
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_2x",
altpll_component.lpm_type = "altpll",
@ -193,8 +193,8 @@ endmodule
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "27.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "67.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "54.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "135.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@ -202,7 +202,7 @@ endmodule
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "13.500"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
@ -278,7 +278,7 @@ endmodule
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "74074"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"

323
rtl/scanconverter.v
View File

@ -83,7 +83,8 @@ wire pclk_1x, pclk_2x, pclk_3x, pclk_4x, pclk_5x;
wire linebuf_rdclock;
wire pclk_act;
wire [1:0] slid_act;
wire [2:0] line_id_act;
wire [2:0] col_id_act;
wire pclk_2x_lock, pclk_3x_lock;
@ -100,15 +101,15 @@ reg DE_pp1, DE_pp2;
wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
wire [11:0] hcnt_act;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_5x, hcnt_4x_aspfix, hcnt_2x_opt, hcnt_3x_opt, hcnt_4x_opt, hcnt_5x_opt, hcnt_5x_hscomp;
reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
reg [2:0] hcnt_2x_opt_ctr, hcnt_3x_opt_ctr, hcnt_4x_opt_ctr, hcnt_5x_opt_ctr;
wire [10:0] vcnt_act;
reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, vcnt_4x, vcnt_5x, vcnt_3x_ref, vcnt_4x_ref, vcnt_5x_ref, lines_1x, lines_2x, lines_4x, lines_5x; //max. 2047
reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, vcnt_4x, vcnt_5x, vcnt_2x_ref, vcnt_3x_ref, vcnt_4x_ref, vcnt_5x_ref, lines_1x, lines_2x, lines_4x, lines_5x; //max. 2047
reg [9:0] vcnt_3x, lines_3x; //max. 1023
reg h_enable_3x_prev4x;
reg DE_3x_prev4x;
reg pclk_1x_prev3x;
reg [1:0] pclk_3x_cnt;
@ -121,11 +122,7 @@ reg pclk_1x_prevprev5x;
reg [2:0] pclk_5x_cnt;
// Data enable
reg h_enable_1x, v_enable_1x;
reg h_enable_2x, v_enable_2x;
reg h_enable_3x, v_enable_3x;
reg h_enable_4x, v_enable_4x;
reg h_enable_5x, v_enable_5x;
reg DE_1x, DE_2x, DE_3x, DE_4x, DE_5x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
@ -136,11 +133,11 @@ reg [2:0] line_out_idx_5x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
reg [10:0] H_ACTIVE; //max. 2047
reg [7:0] H_BACKPORCH; //max. 255
reg [8:0] H_BACKPORCH; //max. 511
reg [10:0] V_ACTIVE; //max. 2047
reg [5:0] V_BACKPORCH; //max. 63
reg [1:0] V_SCANLINEMODE;
reg [1:0] V_SCANLINEID;
reg [4:0] V_SCANLINEID;
reg [7:0] H_SCANLINESTR;
reg [5:0] V_MASK;
reg [2:0] V_MULTMODE;
@ -151,9 +148,10 @@ reg [9:0] H_OPT_STARTOFF;
reg [2:0] H_OPT_SCALE;
reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL;
reg [9:0] H_L5BORDER;
//8 bits per component -> 16.7M colors
reg [7:0] R_1x, G_1x, B_1x, R_pp1, G_pp1, B_pp1, R_pp2, G_pp2, B_pp2;
reg [7:0] R_1x, G_1x, B_1x, R_2x, G_2x, B_2x, R_3x, G_3x, B_3x, R_4x, G_4x, B_4x, R_5x, G_5x, B_5x, R_pp1, G_pp1, B_pp1;
wire [7:0] R_lbuf, G_lbuf, B_lbuf;
wire [7:0] R_act, G_act, B_act;
@ -166,16 +164,16 @@ function [7:0] apply_scanlines;
input [1:0] mode;
input [7:0] data;
input [7:0] str;
input [1:0] actid;
input [1:0] lineid;
input pixid;
input [4:0] mask;
input [2:0] line_id;
input [2:0] col_id;
input fid;
begin
if ((mode == `SCANLINES_H) & (actid == lineid))
if ((mode == `SCANLINES_H) && (mask & (5'h1<<line_id)))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_V) & (actid == pixid))
else if ((mode == `SCANLINES_V) && (5'h0 == col_id))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else if ((mode == `SCANLINES_ALT) & ({actid[1], actid[0]^fid} == lineid))
else if ((mode == `SCANLINES_ALT) && (mask & (5'h1<<(line_id^fid))))
apply_scanlines = (data > str) ? (data-str) : 8'h00;
else
apply_scanlines = data;
@ -186,6 +184,7 @@ function [7:0] apply_scanlines;
function [7:0] apply_mask;
input enable;
input [7:0] data;
input [3:0] brightness;
input [11:0] hoffset;
input [11:0] hstart;
input [11:0] hend;
@ -194,10 +193,9 @@ function [7:0] apply_mask;
input [10:0] vend;
begin
if (enable & ((hoffset < hstart) | (hoffset >= hend) | (voffset < vstart) | (voffset >= vend)))
apply_mask = {2'h0, H_MASK_BR, 2'h0};
apply_mask = {2'h0, brightness, 2'h0};
else
apply_mask = data;
//apply_mask = (hoffset[0] ^ voffset[0]) ? 8'b11111111 : 8'b00000000;
end
endfunction
@ -215,41 +213,57 @@ begin
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
DE_act = (h_enable_1x & v_enable_1x);
DE_act = DE_1x;
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
lines_out = lines_1x;
linebuf_rdclock = 0;
linebuf_hoffset = 0;
pclk_act = pclk_1x;
slid_act = {1'b0, vcnt_1x[0]};
line_id_act = {2'b00, vcnt_1x[0]};
col_id_act = {2'b00, hcnt_1x[0]};
hcnt_act = hcnt_1x;
vcnt_act = vcnt_1x;
end
`V_MULTMODE_2X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
DE_act = (h_enable_2x & v_enable_2x);
R_act = R_2x;
G_act = G_2x;
B_act = B_2x;
DE_act = DE_2x;
HSYNC_act = HSYNC_2x;
VSYNC_act = VSYNC_2x;
lines_out = lines_2x;
linebuf_rdclock = pclk_2x;
linebuf_hoffset = hcnt_2x;
pclk_act = pclk_2x;
slid_act = {line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x};
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
linebuf_hoffset = hcnt_2x;
pclk_act = pclk_2x;
col_id_act = {2'b00, hcnt_2x[0]};
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset = hcnt_2x_opt;
pclk_act = pclk_1x;
col_id_act = {2'b00, hcnt_2x[1]};;
end
default: begin
linebuf_hoffset = hcnt_2x;
pclk_act = pclk_2x;
col_id_act = {2'b00, hcnt_2x[0]};
end
endcase
line_id_act = {1'b0, line_out_idx_2x[1], line_out_idx_2x[0]^FID_1x};
hcnt_act = hcnt_2x;
vcnt_act = vcnt_2x>>1;
vcnt_act = vcnt_2x_ref;
end
`V_MULTMODE_3X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
R_act = R_3x;
G_act = G_3x;
B_act = B_3x;
HSYNC_act = HSYNC_3x;
VSYNC_act = VSYNC_1x;
DE_act = (h_enable_3x & v_enable_3x);
DE_act = DE_3x;
lines_out = {1'b0, lines_3x};
slid_act = line_out_idx_3x;
line_id_act = {1'b0, line_out_idx_3x};
vcnt_act = vcnt_3x_ref;
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
@ -257,36 +271,40 @@ begin
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
col_id_act = {2'b00, hcnt_3x[0]};
end
`H_MULTMODE_ASPECTFIX: begin
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x_aspfix;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x_aspfix;
col_id_act = {2'b00, hcnt_4x[0]};
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x_opt;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
col_id_act = hcnt_3x_opt_ctr;
end
default: begin
linebuf_rdclock = pclk_3x;
linebuf_hoffset = hcnt_3x;
pclk_act = pclk_3x;
hcnt_act = hcnt_3x;
col_id_act = {2'b00, hcnt_3x[0]};
end
endcase
end
`V_MULTMODE_4X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
R_act = R_4x;
G_act = G_4x;
B_act = B_4x;
HSYNC_act = HSYNC_4x;
VSYNC_act = VSYNC_1x;
DE_act = (h_enable_4x & v_enable_4x);
DE_act = DE_4x;
lines_out = lines_4x;
slid_act = line_out_idx_4x;
line_id_act = {1'b0, line_out_idx_4x};
vcnt_act = vcnt_4x_ref;
linebuf_rdclock = pclk_4x;
pclk_act = pclk_4x;
@ -294,37 +312,43 @@ begin
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
linebuf_hoffset = hcnt_4x;
col_id_act = {2'b00, hcnt_4x[0]};
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset = hcnt_4x_opt;
col_id_act = hcnt_4x_opt_ctr;
end
default: begin
linebuf_hoffset = hcnt_4x;
col_id_act = {2'b00, hcnt_4x[0]};
end
endcase
end
`V_MULTMODE_5X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
R_act = R_5x;
G_act = G_5x;
B_act = B_5x;
HSYNC_act = HSYNC_5x;
VSYNC_act = VSYNC_1x;
DE_act = (h_enable_5x & v_enable_5x);
DE_act = DE_5x;
lines_out = lines_5x;
slid_act = line_out_idx_5x;
line_id_act = {2'b00, line_out_idx_5x};
vcnt_act = vcnt_5x_ref;
linebuf_rdclock = pclk_5x;
pclk_act = pclk_5x;
hcnt_act = hcnt_5x;
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
linebuf_hoffset = hcnt_5x;
linebuf_hoffset = hcnt_5x_hscomp;
col_id_act = {2'b00, hcnt_5x[0]};
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset = hcnt_5x_opt;
col_id_act = hcnt_5x_opt_ctr;
end
default: begin
linebuf_hoffset = hcnt_5x;
linebuf_hoffset = hcnt_5x_hscomp;
col_id_act = {2'b00, hcnt_5x[0]};
end
endcase
end
@ -332,20 +356,22 @@ begin
R_act = R_1x;
G_act = G_1x;
B_act = B_1x;
DE_act = (h_enable_1x & v_enable_1x);
DE_act = DE_1x;
HSYNC_act = HSYNC_1x;
VSYNC_act = VSYNC_1x;
lines_out = lines_1x;
linebuf_rdclock = 0;
linebuf_hoffset = 0;
pclk_act = pclk_1x;
slid_act = {1'b0, vcnt_1x[0]};
line_id_act = {2'b00, vcnt_1x[0]};
col_id_act = {2'b00, hcnt_1x[0]};
hcnt_act = hcnt_1x;
vcnt_act = vcnt_1x;
end
endcase
end
//TODO: use single PLL and ALTPLL_RECONFIG
pll_2x pll_linedouble (
.areset ( (V_MULTMODE != `V_MULTMODE_2X) & (V_MULTMODE != `V_MULTMODE_5X) ),
.inclk0 ( PCLK_in ),
@ -384,41 +410,28 @@ begin
HSYNC_pp1 <= 1'b0;
VSYNC_pp1 <= 1'b0;
DE_pp1 <= 1'b0;
R_pp2 <= 8'h00;
G_pp2 <= 8'h00;
B_pp2 <= 8'h00;
HSYNC_pp2 <= 1'b0;
VSYNC_pp2 <= 1'b0;
DE_pp2 <= 1'b0;
R_out <= 8'h00;
G_out <= 8'h00;
G_out <= 8'h00;
B_out <= 8'h00;
HSYNC_out <= 1'b0;
VSYNC_out <= 1'b0;
DE_out <= 1'b0;
end
else
begin
R_pp1 <= R_act;
G_pp1 <= G_act;
B_pp1 <= B_act;
R_pp1 <= apply_scanlines(V_SCANLINEMODE, R_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x);
G_pp1 <= apply_scanlines(V_SCANLINEMODE, G_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x);
B_pp1 <= apply_scanlines(V_SCANLINEMODE, B_act, H_SCANLINESTR, V_SCANLINEID, line_id_act, col_id_act, FID_1x);
HSYNC_pp1 <= HSYNC_act;
VSYNC_pp1 <= VSYNC_act;
DE_pp1 <= DE_act;
R_pp2 <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
G_pp2 <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
B_pp2 <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
HSYNC_pp2 <= HSYNC_act;
VSYNC_pp2 <= VSYNC_act;
DE_pp2 <= DE_act;
R_out <= apply_mask(1, R_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
G_out <= apply_mask(1, G_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
B_out <= apply_mask(1, B_pp2, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
HSYNC_out <= HSYNC_pp2;
VSYNC_out <= VSYNC_pp2;
DE_out <= DE_pp2;
R_out <= apply_mask(1, R_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
G_out <= apply_mask(1, G_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
B_out <= apply_mask(1, B_pp1, H_MASK_BR, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
HSYNC_out <= HSYNC_pp1;
VSYNC_out <= VSYNC_pp1;
DE_out <= DE_pp1;
end
end
@ -482,6 +495,7 @@ begin
H_OPT_SAMPLE_MULT <= 0;
H_OPT_SAMPLE_SEL <= 0;
H_OPT_SCALE <= 0;
H_L5BORDER <= 0;
H_MASK_BR <= 0;
prev_hs <= 0;
prev_vs <= 0;
@ -491,8 +505,7 @@ begin
B_1x <= 8'h00;
HSYNC_1x <= 0;
VSYNC_1x <= 0;
h_enable_1x <= 0;
v_enable_1x <= 0;
DE_1x <= 0;
FID_1x <= 0;
end
else
@ -542,13 +555,19 @@ begin
H_SCANLINESTR <= ((h_info2[22:19]+8'h01)<<4)-1'b1;
V_SCANLINEMODE <= v_info[31:30];
V_SCANLINEID <= v_info[29:28];
case (v_info[26:24])
`V_MULTMODE_1X, `V_MULTMODE_2X: V_SCANLINEID <= (5'b00001 << v_info[28]);
`V_MULTMODE_3X: V_SCANLINEID <= (5'b00001 << {v_info[28], 1'b0});
`V_MULTMODE_4X: V_SCANLINEID <= (5'b00011 << {v_info[28], 1'b0});
`V_MULTMODE_5X: V_SCANLINEID <= (5'b00011 << {2{v_info[28]}});
endcase
H_OPT_STARTOFF <= h_info2[9:0];
H_OPT_SAMPLE_MULT <= h_info2[12:10];
H_OPT_SAMPLE_SEL <= h_info2[15:13];
H_OPT_SCALE <= h_info2[18:16];
H_MASK_BR <= h_info2[26:23];
H_L5BORDER <= h_info2[27] ? (1920-h_info[19:9])/2 : (1600-h_info[19:9])/2;
end
prev_hs <= HSYNC_in;
@ -557,7 +576,11 @@ begin
// record start position of HSYNC
if (`HSYNC_LEADING_EDGE)
HSYNC_start <= hcnt_1x;
// Check if extra vsync needed
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= (lines_1x > ({1'b0, V_ACTIVE} << 1)) ? 1'b1 : 1'b0;
R_1x <= R_in;
G_1x <= G_in;
B_1x <= B_in;
@ -566,12 +589,8 @@ begin
// Ignore possible invalid vsyncs generated by TVP7002
if (vcnt_1x > V_ACTIVE)
VSYNC_1x <= VSYNC_in;
// Check if extra vsync needed
fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] <= (lines_1x > ({1'b0, V_ACTIVE} << 1)) ? 1'b1 : 1'b0;
h_enable_1x <= ((hcnt_1x >= H_BACKPORCH) & (hcnt_1x < H_BACKPORCH + H_ACTIVE));
v_enable_1x <= ((vcnt_1x >= V_BACKPORCH) & (vcnt_1x < V_BACKPORCH + V_ACTIVE)); //- FID_in ???
DE_1x <= ((hcnt_1x >= H_BACKPORCH) & (hcnt_1x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_1x >= V_BACKPORCH) & (vcnt_1x < V_BACKPORCH + V_ACTIVE));
end
end
@ -582,12 +601,17 @@ begin
begin
hcnt_2x <= 0;
vcnt_2x <= 0;
vcnt_2x_ref <= 0;
lines_2x <= 0;
R_2x <= 8'h00;
G_2x <= 8'h00;
B_2x <= 8'h00;
HSYNC_2x <= 0;
VSYNC_2x <= 0;
h_enable_2x <= 0;
v_enable_2x <= 0;
DE_2x <= 0;
line_out_idx_2x <= 0;
hcnt_2x_opt <= 0;
hcnt_2x_opt_ctr <= 0;
end
else
begin
@ -595,32 +619,53 @@ begin
begin
hcnt_2x <= 0;
line_out_idx_2x <= 0;
hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
hcnt_2x_opt_ctr <= 0;
end
else if (hcnt_2x == hmax[~line_idx]) //line_idx_prev?
else if (hcnt_2x == hmax[~line_idx])
begin
hcnt_2x <= 0;
line_out_idx_2x <= line_out_idx_2x + 1'b1;
hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
hcnt_2x_opt_ctr <= 0;
end
else
hcnt_2x <= hcnt_2x + 1'b1;
if ((pclk_1x == 1'b0) & (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1))
begin
if (`VSYNC_TRAILING_EDGE)
vcnt_2x <= 0;
else if (vcnt_2x == lines_1x)
hcnt_2x <= hcnt_2x + 1'b1;
if (hcnt_2x >= H_OPT_STARTOFF)
begin
vcnt_2x <= 0;
lines_2x <= vcnt_2x;
if (hcnt_2x_opt_ctr == H_OPT_SCALE-1'b1)
begin
hcnt_2x_opt <= hcnt_2x_opt + H_OPT_SAMPLE_MULT;
hcnt_2x_opt_ctr <= 0;
end
else
hcnt_2x_opt_ctr <= hcnt_2x_opt_ctr + 1'b1;
end
end
else if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
if ((pclk_1x == 1'b0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //aligned with posedge of pclk_1x
begin
vcnt_2x <= 0;
lines_2x <= vcnt_2x;
vcnt_2x_ref <= 0;
if (fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b0)
lines_2x <= vcnt_2x;
end
else if (hcnt_2x == hmax[~line_idx])
vcnt_2x <= vcnt_2x + 1'b1;
begin
if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT] == 1'b1) & (vcnt_2x == lines_1x-1))
begin
vcnt_2x <= 0;
vcnt_2x_ref <= 0;
lines_2x <= lines_1x;
end
else
begin
vcnt_2x <= vcnt_2x + 1'b1;
if (line_out_idx_2x == 1)
vcnt_2x_ref <= vcnt_2x_ref + 1'b1;
end
end
if (pclk_1x == 1'b0)
begin
@ -630,10 +675,12 @@ begin
VSYNC_2x <= VSYNC_in;
end
R_2x <= R_lbuf;
G_2x <= G_lbuf;
B_2x <= B_lbuf;
HSYNC_2x <= ~(hcnt_2x >= HSYNC_start);
h_enable_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE));
v_enable_2x <= ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1)));
DE_2x <= ((hcnt_2x >= H_BACKPORCH) & (hcnt_2x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_2x >= (V_BACKPORCH<<1)) & (vcnt_2x < ((V_BACKPORCH + V_ACTIVE)<<1)));
end
end
@ -645,9 +692,11 @@ begin
vcnt_3x <= 0;
vcnt_3x_ref <= 0;
lines_3x <= 0;
R_3x <= 8'h00;
G_3x <= 8'h00;
B_3x <= 8'h00;
HSYNC_3x <= 0;
h_enable_3x <= 0;
v_enable_3x <= 0;
DE_3x <= 0;
pclk_3x_cnt <= 0;
pclk_1x_prev3x <= 0;
line_out_idx_3x <= 0;
@ -663,7 +712,7 @@ begin
hcnt_3x_opt <= H_OPT_SAMPLE_SEL;
hcnt_3x_opt_ctr <= 0;
end
else if (hcnt_3x == hmax[~line_idx]) //line_idx_prev?
else if (hcnt_3x == hmax[~line_idx])
begin
hcnt_3x <= 0;
line_out_idx_3x <= line_out_idx_3x + 1'b1;
@ -698,11 +747,6 @@ begin
vcnt_3x_ref <= vcnt_3x_ref + 1'b1;
end
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
//TODO: VSYNC_3x
h_enable_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE));
v_enable_3x <= ((vcnt_3x_ref >= V_BACKPORCH) & (vcnt_3x_ref < V_BACKPORCH + V_ACTIVE));
//track pclk_3x alignment to pclk_1x rising edge (pclk_1x=1 @ 120deg & pclk_1x=0 @ 240deg)
if (((pclk_1x_prev3x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_3x_cnt == 2'h2))
pclk_3x_cnt <= 0;
@ -710,6 +754,14 @@ begin
pclk_3x_cnt <= pclk_3x_cnt + 1'b1;
pclk_1x_prev3x <= pclk_1x;
R_3x <= R_lbuf;
G_3x <= G_lbuf;
B_3x <= B_lbuf;
HSYNC_3x <= ~(hcnt_3x >= HSYNC_start);
//TODO: VSYNC_3x
DE_3x <= ((hcnt_3x >= H_BACKPORCH) & (hcnt_3x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_3x_ref >= V_BACKPORCH) & (vcnt_3x_ref < V_BACKPORCH + V_ACTIVE));
end
end
@ -718,14 +770,16 @@ begin
if (!reset_n)
begin
hcnt_4x_aspfix <= 0;
h_enable_3x_prev4x <= 0;
DE_3x_prev4x <= 0;
hcnt_4x <= 0;
vcnt_4x <= 0;
vcnt_4x_ref <= 0;
lines_4x <= 0;
R_4x <= 8'h00;
G_4x <= 8'h00;
B_4x <= 8'h00;
HSYNC_4x <= 0;
h_enable_4x <= 0;
v_enable_4x <= 0;
DE_4x <= 0;
pclk_4x_cnt <= 0;
pclk_1x_prev4x <= 0;
line_out_idx_4x <= 0;
@ -734,13 +788,13 @@ begin
end
else
begin
// Can we sync reliably to h_enable_3x???
if ((h_enable_3x == 1) & (h_enable_3x_prev4x == 0))
// TODO: better implementation
if ((DE_3x == 1) & (DE_3x_prev4x == 0))
hcnt_4x_aspfix <= hcnt_3x - 160;
else
hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1;
h_enable_3x_prev4x <= h_enable_3x;
DE_3x_prev4x <= DE_3x;
if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //aligned with posedge of pclk_1x
@ -750,7 +804,7 @@ begin
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
hcnt_4x_opt_ctr <= 0;
end
else if (hcnt_4x == hmax[~line_idx]) //line_idx_prev?
else if (hcnt_4x == hmax[~line_idx])
begin
hcnt_4x <= 0;
line_out_idx_4x <= line_out_idx_4x + 1'b1;
@ -785,11 +839,6 @@ begin
vcnt_4x_ref <= vcnt_4x_ref + 1'b1;
end
HSYNC_4x <= ~(hcnt_4x >= HSYNC_start);
//TODO: VSYNC_4x
h_enable_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE));
v_enable_4x <= ((vcnt_4x_ref >= V_BACKPORCH) & (vcnt_4x_ref < V_BACKPORCH + V_ACTIVE));
//track pclk_4x alignment to pclk_1x rising edge (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
@ -797,6 +846,14 @@ begin
pclk_4x_cnt <= pclk_4x_cnt + 1'b1;
pclk_1x_prev4x <= pclk_1x;
R_4x <= R_lbuf;
G_4x <= G_lbuf;
B_4x <= B_lbuf;
HSYNC_4x <= ~(hcnt_4x >= HSYNC_start);
//TODO: VSYNC_4x
DE_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE)) & ((vcnt_4x_ref >= V_BACKPORCH) & (vcnt_4x_ref < V_BACKPORCH + V_ACTIVE));
end
end
@ -808,15 +865,18 @@ begin
vcnt_5x <= 0;
vcnt_5x_ref <= 0;
lines_5x <= 0;
R_5x <= 8'h00;
G_5x <= 8'h00;
B_5x <= 8'h00;
HSYNC_5x <= 0;
h_enable_5x <= 0;
v_enable_5x <= 0;
DE_5x <= 0;
pclk_5x_cnt <= 0;
pclk_1x_prev5x <= 0;
pclk_1x_prevprev5x <= 0;
line_out_idx_5x <= 0;
hcnt_5x_opt <= 0;
hcnt_5x_opt_ctr <= 0;
hcnt_5x_hscomp <= 0;
end
else
begin
@ -824,14 +884,14 @@ begin
begin
hcnt_5x <= 0;
line_out_idx_5x <= 0;
hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
hcnt_5x_opt <= 120 + H_OPT_SAMPLE_SEL;
hcnt_5x_opt_ctr <= 0;
end
else if (hcnt_5x == hmax[~line_idx]) //line_idx_prev?
else if (hcnt_5x == hmax[~line_idx])
begin
hcnt_5x <= 0;
line_out_idx_5x <= line_out_idx_5x + 1'b1;
hcnt_5x_opt <= H_OPT_SAMPLE_SEL;
hcnt_5x_opt <= 120 + H_OPT_SAMPLE_SEL;
hcnt_5x_opt_ctr <= 0;
end
else
@ -862,11 +922,6 @@ begin
vcnt_5x_ref <= vcnt_5x_ref + 1'b1;
end
HSYNC_5x <= ~(hcnt_5x >= HSYNC_start);
//TODO: VSYNC_5x
h_enable_5x <= ((hcnt_5x >= H_BACKPORCH-96) & (hcnt_5x < H_BACKPORCH + H_ACTIVE + 96));
v_enable_5x <= ((vcnt_5x_ref >= V_BACKPORCH) & (vcnt_5x_ref < V_BACKPORCH + V_ACTIVE));
//track pclk_5x alignment to pclk_1x rising edge (pclk_1x=1 @ 144deg & pclk_1x=0 @ 216deg & pclk_1x=0 @ 288deg)
if (((pclk_1x_prevprev5x == 1'b1) & (pclk_1x_prev5x == 1'b0)) | (pclk_5x_cnt == 3'h4))
pclk_5x_cnt <= 0;
@ -875,6 +930,16 @@ begin
pclk_1x_prev5x <= pclk_1x;
pclk_1x_prevprev5x <= pclk_1x_prev5x;
hcnt_5x_hscomp <= hcnt_5x + 121;
R_5x <= R_lbuf;
G_5x <= G_lbuf;
B_5x <= B_lbuf;
HSYNC_5x <= ~(hcnt_5x >= HSYNC_start);
//TODO: VSYNC_5x
DE_5x <= ((hcnt_5x >= H_BACKPORCH - H_L5BORDER) & (hcnt_5x < H_BACKPORCH + H_ACTIVE + H_L5BORDER)) & ((vcnt_5x_ref >= V_BACKPORCH) & (vcnt_5x_ref < V_BACKPORCH + V_ACTIVE));
end
end

1864
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
View File

File diff suppressed because it is too large Load Diff

90
software/sys_controller/ossc/av_controller.c
View File

@ -92,12 +92,10 @@ inline void SetupAudio(tx_mode_t mode)
EnableAudioInfoFrame(FALSE, NULL);
if (tc.tx_mode == TX_HDMI) {
alt_u32 pclk_out = (TVP_EXTCLK_HZ/cm.clkcnt)*video_modes[cm.id].h_total;
// TODO: check pixel repetition
if (video_modes[cm.id].flags & MODE_L2ENABLE)
alt_u32 pclk_out = (TVP_EXTCLK_HZ/cm.clkcnt)*video_modes[cm.id].h_total*cm.sample_mult*(cm.fpga_vmultmode+1);
if (cm.hdmitx_pixelrep == HDMITX_PIXELREP_2X)
pclk_out *= 2;
else if (video_modes[cm.id].flags & (MODE_L3_MODE0|MODE_L3_MODE1|MODE_L3_MODE2|MODE_L3_MODE3))
pclk_out *= 3;
printf("PCLK_out: %luHz\n", pclk_out);
EnableAudioOutput4OSSC(pclk_out, tc.audio_dw_sampl, tc.audio_swap_lr);
@ -269,23 +267,20 @@ status_t get_status(tvp_input_t input, video_format format)
(tc.pm_384p != cm.cc.pm_384p) ||
(tc.pm_480i != cm.cc.pm_480i) ||
(tc.pm_480p != cm.cc.pm_480p) ||
(tc.pm_1080i != cm.cc.pm_1080i) ||
(tc.l3_mode != cm.cc.l3_mode) ||
(tc.l4_mode != cm.cc.l4_mode) ||
(tc.l5_mode != cm.cc.l5_mode))
(tc.l5_mode != cm.cc.l5_mode) ||
(tc.l5_fmt != cm.cc.l5_fmt) ||
(tc.tvp_hpll2x != cm.cc.tvp_hpll2x))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
if ((tc.s480p_mode != cm.cc.s480p_mode) && ((video_modes[cm.id].group == GROUP_DTV480P) || (video_modes[cm.id].group == GROUP_VGA480P)))
status = (status < MODE_CHANGE) ? MODE_CHANGE : status;
if (update_cur_vm) {
if (video_modes[cm.id].flags & MODE_PLLDIVBY2)
h_samplerate = 2*video_modes[cm.id].h_total;
else
h_samplerate = video_modes[cm.id].h_total;
tvp_writereg(TVP_HPLLDIV_LSB, ((h_samplerate & 0xf) << 4));
tvp_writereg(TVP_HPLLDIV_MSB, (h_samplerate >> 4));
tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen);
tvp_setup_hpll(cm.sample_mult*video_modes[cm.id].h_total, clkcnt, cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2));
tvp_writereg(TVP_HSOUTWIDTH, cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut);
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
}
@ -302,7 +297,7 @@ status_t get_status(tvp_input_t input, video_format format)
(tc.h_mask != cm.cc.h_mask) ||
(tc.v_mask != cm.cc.v_mask) ||
(tc.mask_br != cm.cc.mask_br) ||
(tc.l3m3_hmult != cm.cc.l3m3_hmult))
(tc.ar_256col != cm.cc.ar_256col))
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
if (tc.sampler_phase != cm.cc.sampler_phase) {
@ -351,27 +346,23 @@ status_t get_status(tvp_input_t input, video_format format)
return status;
}
// h_info: [31:30] [29:20] [19:9] [8] [7:0]
// | H_MULTMODE[1:0] | H_MASK[9:0] | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] |
// h_info: [31:30] [29:20] [19:9] [8:0]
// | H_MULTMODE[1:0] | H_MASK[9:0] | H_ACTIVE[10:0] | H_BACKPORCH[8:0] |
//
// h_info2: [31:27] [26:23] [22:19] [18:16] [15:13] [12:10] [9:0]
// | | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
// h_info2: [31:28] [27] [26:23] [22:19] [18:16] [15:13] [12:10] [9:0]
// | | H_L5FMT | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
//
// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0]
// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
//
void set_videoinfo()
{
alt_u8 slid_target;
alt_u8 sl_mode_fpga;
alt_u8 h_opt_scale = 1;
alt_u16 h_opt_startoffs = 0;
alt_u16 h_border, h_mask;
if (cm.fpga_vmultmode == FPGA_V_MULTMODE_3X)
slid_target = cm.cc.sl_id ? (cm.cc.sl_type == 1 ? 1 : 2) : 0;
else
slid_target = cm.cc.sl_id;
alt_u16 v_active = video_modes[cm.id].v_active;
alt_u16 v_backporch = video_modes[cm.id].v_backporch;
if (cm.cc.sl_mode == 2) { //manual
sl_mode_fpga = 1+cm.cc.sl_type;
@ -387,18 +378,40 @@ void set_videoinfo()
}
switch (cm.target_lm) {
case MODE_L2:
h_opt_scale = cm.sample_mult;
break;
case MODE_L3_320_COL:
case MODE_L5_256_COL:
h_opt_scale = 3;
break;
case MODE_L3_256_COL:
h_opt_scale = cm.cc.l3m3_hmult;
h_opt_scale = 4-cm.cc.ar_256col;
break;
case MODE_L4_320_COL:
h_opt_scale = 4;
break;
case MODE_L4_256_COL:
h_opt_scale = 5-cm.cc.ar_256col;
break;
case MODE_L5_GEN_4_3:
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
case MODE_L5_320_COL:
h_opt_scale = 5;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
case MODE_L5_256_COL:
h_opt_scale = 6-cm.cc.ar_256col;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
default:
break;
@ -406,13 +419,13 @@ void set_videoinfo()
h_border = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2);
h_mask = h_border + h_opt_scale*cm.cc.h_mask;
h_opt_startoffs = h_border + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*video_modes[cm.id].h_backporch) / cm.sample_mult);
h_opt_startoffs = h_border + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch) / cm.sample_mult);
h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult;
printf("h_opt_startoffs: %u\n", h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.fpga_hmultmode<<30) | (h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (cm.cc.mask_br<<23) | (cm.cc.sl_str<<19) | (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.fpga_hmultmode<<30) | (h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, ((cm.cc.l5_fmt!=L5FMT_1600x1200)<<27) | (cm.cc.mask_br<<23) | (cm.cc.sl_str<<19) | (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (cm.cc.sl_id<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (v_active<<7) | v_backporch);
}
// Configure TVP7002 and scan converter logic based on the video mode
@ -454,11 +467,19 @@ void program_mode()
vm_sel = cm.id;
target_type = target_typemask & video_modes[cm.id].type;
h_synclen_px = ((alt_u32)h_syncinlen * (alt_u32)video_modes[cm.id].h_total) / cm.clkcnt;
h_synclen_px = ((alt_u32)h_syncinlen * (alt_u32)video_modes[cm.id].h_total*cm.sample_mult) / cm.clkcnt;
printf("Mode %s selected - hsync width: %upx\n", video_modes[cm.id].name, (unsigned)h_synclen_px);
tvp_source_setup(cm.id, target_type, (cm.progressive ? cm.totlines : cm.totlines/2), v_hz_x100/100, (alt_u8)h_synclen_px, cm.cc.pre_coast, cm.cc.post_coast, cm.cc.vsync_thold, cm.sample_mult);
tvp_source_setup(target_type,
cm.sample_mult*video_modes[cm.id].h_total,
cm.clkcnt,
cm.cc.tvp_hpll2x && (video_modes[cm.id].flags & MODE_PLLDIVBY2),
(alt_u8)h_synclen_px,
cm.sample_mult*video_modes[cm.id].h_synclen-cm.hsync_cut,
cm.cc.pre_coast,
cm.cc.post_coast,
cm.cc.vsync_thold);
set_lpf(cm.cc.video_lpf);
cm.sample_sel = tvp_set_hpll_phase(cm.cc.sampler_phase, cm.sample_mult);
@ -466,6 +487,9 @@ void program_mode()
set_videoinfo();
// TX re-init skipped to minimize mode switch delay
//TX_enable(cm.cc.tx_mode);
#ifdef DIY_AUDIO
#ifdef MANUAL_CTS
SetupAudio(cm.cc.tx_mode);

1
software/sys_controller/ossc/av_controller.h
View File

@ -98,6 +98,7 @@ typedef struct {
alt_u8 hdmitx_pixr_ifr;
alt_u8 sample_mult;
alt_u8 sample_sel;
alt_u8 hsync_cut;
mode_flags target_lm;
avinput_t avinput;
// Current configuration

3
software/sys_controller/ossc/avconfig.c
View File

@ -45,7 +45,8 @@ const avconfig_t tc_default = {
.pm_240p = 1,
.pm_384p = 1,
.pm_480i = 1,
.l3m3_hmult = 4,
.pm_1080i = 1,
.tvp_hpll2x = 1,
.sampler_phase = DEFAULT_SAMPLER_PHASE,
.sync_vth = DEFAULT_SYNC_VTH,
.linelen_tol = DEFAULT_LINELEN_TOL,

9
software/sys_controller/ossc/avconfig.h
View File

@ -37,6 +37,10 @@
#define SL_MODE_MAX 2
#define SL_TYPE_MAX 2
#define L5FMT_1920x1080 0
#define L5FMT_1600x1200 1
#define L5FMT_1920x1200 2
typedef struct {
alt_u8 sl_mode;
alt_u8 sl_type;
@ -46,17 +50,20 @@ typedef struct {
alt_u8 l3_mode;
alt_u8 l4_mode;
alt_u8 l5_mode;
alt_u8 l5_fmt;
alt_u8 pm_240p;
alt_u8 pm_384p;
alt_u8 pm_480i;
alt_u8 pm_480p;
alt_u8 l3m3_hmult;
alt_u8 pm_1080i;
alt_u8 ar_256col;
alt_u8 h_mask;
alt_u8 v_mask;
alt_u8 mask_br;
alt_u8 tx_mode;
alt_u8 s480p_mode;
alt_u8 sampler_phase;
alt_u8 tvp_hpll2x;
alt_u8 ypbpr_cs;
alt_u8 sync_vth;
alt_u8 linelen_tol;

23
software/sys_controller/ossc/menu.c
View File

@ -49,12 +49,12 @@ static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" };
static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480p", "VESA 640x480@60" };
static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l5_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l4l5_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_384p_desc[] = { "Passthru", "Line2x" };
static const char *pm_480i_desc[] = { "Passthru", "Line2x" };
static const char *pm_480p_desc[] = { "Passthru", "Line2x" };
static const char *pm_480i_desc[] = { "Passthru", "Line2x (bob)" };
static const char *pm_384p_480p_desc[] = { "Passthru", "Line2x" };
static const char *ar_256col_desc[] = { "4:3", "8:7" };
static const char *tx_mode_desc[] = { "HDMI", "DVI" };
static const char *sl_mode_desc[] = { LNG("Off","ｵﾌ"), LNG("Auto","ｼﾞﾄﾞｳ"), LNG("Manual","ｼｭﾄﾞｳ") };
static const char *sl_type_desc[] = { LNG("Horizontal","ｽｲﾍｲ"), LNG("Vertical","ｽｲﾁｮｸ"), LNG("Alternating","ｺｳｺﾞ") };
@ -94,6 +94,7 @@ MENU(menu_vinputproc, P99_PROTECT({ \
MENU(menu_sampling, P99_PROTECT({ \
{ LNG("Sampling phase","ｻﾝﾋﾌﾟﾘﾝｸﾞﾌｪｰｽﾞ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.sampler_phase, OPT_WRAP, 0, SAMPLER_PHASE_MAX, sampler_phase_disp } } },
{ LNG("480p in sampler","ｻﾝﾌﾟﾗｰﾆ480p"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.s480p_mode, OPT_WRAP, SETTING_ITEM(s480p_mode_desc) } } },
{ "Allow TVP HPLL2x", OPT_AVCONFIG_SELECTION, { .sel = { &tc.tvp_hpll2x, OPT_WRAP, SETTING_ITEM(off_on_desc) } } },
{ LNG("<Adv. timing >","<ｶｸｼｭﾀｲﾐﾝｸﾞ>"), OPT_SUBMENU, { .sub = { &menu_advtiming, vm_display } } },
}))
@ -108,13 +109,15 @@ MENU(menu_sync, P99_PROTECT({ \
MENU(menu_output, P99_PROTECT({ \
{ "240p/288p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
{ "384p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
{ "384p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } },
{ "480i/576i proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
{ "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
{ "480p/576p proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } },
{ "960i/1080i proc", OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
{ "Line3x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },
{ "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4_mode_desc) } } },
{ "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l5_mode_desc) } } },
{ "256x240 L3_Hmult", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.l3m3_hmult, OPT_NOWRAP, 1, 5, value_disp } } },
{ "Line4x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l4_mode, OPT_WRAP, SETTING_ITEM(l4l5_mode_desc) } } },
{ "Line5x mode", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_mode, OPT_WRAP, SETTING_ITEM(l4l5_mode_desc) } } },
{ "Line5x format", OPT_AVCONFIG_SELECTION, { .sel = { &tc.l5_fmt, OPT_WRAP, SETTING_ITEM(l5_fmt_desc) } } },
{ "256x240 aspect", OPT_AVCONFIG_SELECTION, { .sel = { &tc.ar_256col, OPT_WRAP, SETTING_ITEM(ar_256col_desc) } } },
{ LNG("TX mode","TXﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.tx_mode, OPT_WRAP, SETTING_ITEM(tx_mode_desc) } } },
{ LNG("Initial input","ｼｮｷﾆｭｳﾘｮｸ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.def_input, OPT_WRAP, SETTING_ITEM(avinput_str) } } },
}))

14
software/sys_controller/tvp7002/tvp7002.c
View File

@ -41,8 +41,6 @@ const ypbpr_to_rgb_csc_t csc_coeffs[] = {
static const alt_u8 Kvco[] = {75, 85, 150, 200};
static const char *Kvco_str[] = { "Ultra low", "Low", "Medium", "High" };
extern mode_data_t video_modes[];
static void tvp_set_clamp(video_format fmt)
{
switch (fmt) {
@ -201,7 +199,7 @@ void tvp_set_fine_gain_offset(color_setup_t *col) {
}
// Configure H-PLL (sampling rate, VCO gain and charge pump current)
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2)
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2)
{
alt_u32 pclk_est;
alt_u8 vco_range;
@ -210,7 +208,7 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 pll
alt_u8 status = tvp_readreg(TVP_HPLLPHASE) & 0xF8;
// Enable PLL post-div-by-2 with double samplerate
if (plldivby2) {
if (plldivby2 && (h_samplerate < 2048)) {
tvp_writereg(TVP_HPLLPHASE, status|1);
h_samplerate = 2*h_samplerate;
} else {
@ -222,7 +220,7 @@ void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 pll
printf("Horizontal samplerate set to %u\n", h_samplerate);
pclk_est = ((alt_u32)h_samplerate * v_lines * hz) / 1000; //in kHz
pclk_est = ((alt_u32)h_samplerate * (TVP_EXTCLK_HZ/(alt_u32)refclks_per_line)) / 1000; //in kHz
printf("Estimated PCLK_HPLL: %lu.%.3lu MHz\n", pclk_est/1000, pclk_est%1000);
@ -343,7 +341,7 @@ void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen)
}
}
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult)
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold)
{
// Clamp position and ALC
tvp_set_clamp_position(type, h_syncinlen);
@ -367,13 +365,13 @@ void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz,
break;
}
tvp_setup_hpll(video_modes[modeid].h_total, vlines, hz, !!(video_modes[modeid].flags & MODE_PLLDIVBY2));
tvp_setup_hpll(h_samplerate, refclks_per_line, plldivby2);
// Default (3,3) coast may lead to PLL jitter and sync loss (e.g. SNES)
tvp_set_hpllcoast(pre_coast, post_coast);
// Hsync output width
tvp_writereg(TVP_HSOUTWIDTH, sample_mult*video_modes[modeid].h_synclen);
tvp_writereg(TVP_HSOUTWIDTH, h_syncoutlen);
}
void tvp_source_sel(tvp_input_t input, video_format fmt)

4
software/sys_controller/tvp7002/tvp7002.h
View File

@ -84,7 +84,7 @@ void tvp_init();
void tvp_set_fine_gain_offset(color_setup_t *col);
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 v_lines, alt_u8 hz, alt_u8 plldivby2);
void tvp_setup_hpll(alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2);
void tvp_sel_clk(tvp_refclk_t refclk);
@ -100,7 +100,7 @@ void tvp_set_sog_thold(alt_u8 val);
void tvp_set_alc(alt_u8 en_alc, video_type type, alt_u8 h_syncinlen);
void tvp_source_setup(alt_8 modeid, video_type type, alt_u32 vlines, alt_u8 hz, alt_u8 h_syncinlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold, alt_u8 sample_mult);
void tvp_source_setup(video_type type, alt_u16 h_samplerate, alt_u16 refclks_per_line, alt_u8 plldivby2, alt_u8 h_syncinlen, alt_u16 h_syncoutlen, alt_u8 pre_coast, alt_u8 post_coast, alt_u8 vsync_thold);
void tvp_source_sel(tvp_input_t input, video_format fmt);

29
software/sys_controller/tvp7002/video_modes.c
View File

@ -41,7 +41,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
alt_u8 pt_only = 0;
// one for each video_group
alt_u8* group_ptr[] = { &pt_only, &cm.cc.pm_240p, &cm.cc.pm_384p, &cm.cc.pm_480i, &cm.cc.pm_480p, &cm.cc.pm_480p };
alt_u8* group_ptr[] = { &pt_only, &cm.cc.pm_240p, &cm.cc.pm_384p, &cm.cc.pm_480i, &cm.cc.pm_480p, &cm.cc.pm_480p, &cm.cc.pm_1080i };
for (i=0; i<num_modes; i++) {
mode_type = video_modes[i].type;
@ -57,7 +57,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
mode_type &= ~VIDEO_EDTV;
else if (cm.cc.s480p_mode == 1) // DTV 480P
continue;
} else if (video_modes[i].group > GROUP_VGA480P) {
} else if (video_modes[i].group > GROUP_1080I) {
printf("WARNING: Corrupted mode (id %d)\n", i);
continue;
}
@ -70,6 +70,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.hdmitx_pixelrep = HDMITX_PIXELREP_DISABLE;
cm.hdmitx_pixr_ifr = 0;
cm.sample_mult = 1;
cm.hsync_cut = 0;
cm.target_lm = target_lm;
switch (target_lm) {
@ -81,8 +82,16 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
break;
case MODE_L2:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hdmitx_pixelrep = ((video_modes[i].group == GROUP_DTV480P) || (video_modes[i].group == GROUP_VGA480P)) ? HDMITX_PIXELREP_2X : HDMITX_PIXELREP_DISABLE;
if ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I)) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
} else {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
}
cm.hdmitx_pixelrep = ((video_modes[i].group == GROUP_384P) ||
(video_modes[i].group == GROUP_DTV480P) ||
(video_modes[i].group == GROUP_VGA480P) ||
((video_modes[i].group == GROUP_1080I) && (video_modes[i].h_total < 1200))) ? HDMITX_PIXELREP_2X : HDMITX_PIXELREP_DISABLE;
break;
case MODE_L3_GEN_16_9:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
@ -119,13 +128,19 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
case MODE_L5_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
cm.hsync_cut = 120;
break;
case MODE_L5_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
cm.hsync_cut = 120;
break;
case MODE_L5_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.hdmitx_pixelrep = HDMITX_PIXELREP_2X;
cm.sample_mult = 3;
cm.sample_mult = 6;
cm.hsync_cut = 120;
break;
default:
printf("WARNING: invalid target_lm\n");

21
software/sys_controller/tvp7002/video_modes.h
View File

@ -58,6 +58,7 @@ typedef enum {
GROUP_480I = 3,
GROUP_DTV480P = 4,
GROUP_VGA480P = 5,
GROUP_1080I = 6,
} video_group;
typedef enum {
@ -74,7 +75,8 @@ typedef enum {
MODE_L4_320_COL = (1<<9),
MODE_L4_256_COL = (1<<10),
MODE_L5_GEN_4_3 = (1<<11),
MODE_L5_256_COL = (1<<12),
MODE_L5_320_COL = (1<<12),
MODE_L5_256_COL = (1<<13),
} mode_flags;
typedef struct {
@ -97,18 +99,17 @@ typedef struct {
{ "1280x240", 1280, 240, 6000, 1560, 262, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 6000, 1170, 262, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
/*{ "240p_L3M2", 384, 240, 6000, 512, 262, 66, 16, 31, 3, (VIDEO_LDTV|VIDEO_PC), (MODE_L3_MODE2|MODE_PLLDIVBY2) }, //CPS2*/ \
{ "320x240", 320, 240, 6000, 4*426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
{ "256x240", 256, 240, 6000, 5*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
{ "256x216", 256, 216, 6000, 3*341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, MODE_L5_256_COL }, \
{ "320x240", 320, 240, 6000, 426, 262, 49, 16, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL | MODE_PLLDIVBY2) }, \
{ "256x240", 256, 240, 6000, 341, 262, 39, 16, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL | MODE_PLLDIVBY2) }, \
{ "240p", 720, 240, 6000, 858, 262, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "768*216", 768, 216, 6000, 1023, 262, 117, 16, 75, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3) }, \
{ "1536*240", 1536, 240, 6000, 2046, 262, 234, 16, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 5000, 1560, 312, 170, 16, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 5000, 1170, 312, 128, 16, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "320x240LB", 320, 240, 5000, 4*426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL) }, \
{ "256x240LB", 256, 240, 5000, 5*341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL) }, \
{ "320x240LB", 320, 240, 5000, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_320_COL | MODE_L4_320_COL | MODE_PLLDIVBY2) }, \
{ "256x240LB", 256, 240, 5000, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_256_COL | MODE_L4_256_COL | MODE_PLLDIVBY2) }, \
{ "288p", 720, 288, 5000, 864, 312, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "384p", 496, 384, 5766, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* Sega Model 2 */ \
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2) }, /* X68k @ 24kHz */ \
{ "640x384", 640, 384, 5500, 800, 492, 48, 63, 96, 2, VIDEO_PC, GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, /* X68k @ 24kHz */ \
{ "480i", 720, 240, 5994, 858, 525, 65, 16, 60, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_480I, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2 | MODE_INTERLACED) }, \
{ "480p", 720, 480, 5994, 858, 525, 60, 30, 62, 6, (VIDEO_EDTV | VIDEO_PC), GROUP_DTV480P, (MODE_PT | MODE_L2) }, \
{ "640x480", 640, 480, 6000, 800, 525, 48, 33, 96, 2, (VIDEO_PC | VIDEO_EDTV), GROUP_VGA480P, (MODE_PT | MODE_L2) }, \
@ -120,9 +121,11 @@ typedef struct {
{ "1280x720", 1280, 720, 6000, 1650, 750, 220, 20, 40, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1024x768", 1024, 768, 6000, 1344, 806, 160, 29, 136, 6, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1280x1024", 1280, 1024, 6000, 1688, 1066, 248, 38, 112, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1080i", 1920, 1080, 5994, 2200, 1125, 148, 16, 44, 5, VIDEO_HDTV, GROUP_NONE, (MODE_PT | MODE_INTERLACED) }, /* Too high freq for L2 PLL */ \
{ "640x960i", 640, 480, 5994, 800, 1050, 48, 33, 96, 2, (VIDEO_EDTV | VIDEO_PC), GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080i", 1920, 540, 5994, 2200, 1125, 188, 16, 44, 5, VIDEO_HDTV, GROUP_1080I, (MODE_PT | MODE_L2 | MODE_INTERLACED) }, \
{ "1080p", 1920, 1080, 5994, 2200, 1125, 188, 36, 44, 5, VIDEO_HDTV, GROUP_NONE, MODE_PT }, \
{ "1920x1080", 1920, 1080, 6000, 2200, 1125, 148, 36, 44, 5, VIDEO_PC, GROUP_NONE, MODE_PT }, \
{ "1600x1200", 1600, 1200, 6000, 2160, 1250, 255, 46, 192, 3, VIDEO_PC, GROUP_NONE, MODE_PT }, \
}
#define VIDEO_MODES_SIZE (sizeof((mode_data_t[])VIDEO_MODES_DEF))

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Jan 29, 2017 12:54:52 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1485687292131</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Feb 7, 2017 10:49:51 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1486500591240</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 16.1 196 (Future versions may contain additional information.) -->
<!-- 2017.01.29.12:52:45 -->
<!-- 2017.02.07.22:47:41 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1485687165</value>
<value>1486500460</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>