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free up 1 M9K by modifying altera_jtag_avalon_master
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marqs
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package require -exact sopc 9.1
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# +-----------------------------------
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# | module altera_jtag_avalon_master_mod
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# |
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set_module_property NAME altera_jtag_avalon_master_mod
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set_module_property DESCRIPTION "The JTAG to Avalon Master Bridge is a collection of pre-wired components that provide an Avalon Master using the new JTAG channel."
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set_module_property VERSION "17.1"
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set_module_property GROUP "Basic Functions/Bridges and Adaptors/Memory Mapped"
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set_module_property AUTHOR "Altera Corporation"
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set_module_property DISPLAY_NAME "JTAG to Avalon Master Bridge (customized)"
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set_module_property DATASHEET_URL "http://www.altera.com/literature/hb/nios2/qts_qii55011.pdf"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property EDITABLE false
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set_module_property ANALYZE_HDL false
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set_module_property VALIDATION_CALLBACK validate
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set_module_property COMPOSE_CALLBACK compose
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set_module_assignment debug.hostConnection {type jtag id 110:132}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | parameters
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# |
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add_parameter USE_PLI INTEGER 0
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set_parameter_property USE_PLI DISPLAY_NAME "Use Simulation Link Mode"
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set_parameter_property USE_PLI DISPLAY_HINT boolean
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set_parameter_property USE_PLI UNITS None
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set_parameter_property USE_PLI HDL_PARAMETER true
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add_parameter PLI_PORT INTEGER 50000
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set_parameter_property PLI_PORT DISPLAY_NAME "Simulation Link Server Port"
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set_parameter_property PLI_PORT UNITS None
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set_parameter_property PLI_PORT VISIBLE true
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set_parameter_property PLI_PORT ENABLED false
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set_parameter_property PLI_PORT HDL_PARAMETER true
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add_parameter COMPONENT_CLOCK INTEGER 0
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set_parameter_property COMPONENT_CLOCK SYSTEM_INFO { CLOCK_RATE clock }
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set_parameter_property COMPONENT_CLOCK VISIBLE false
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add_parameter FAST_VER "INTEGER" "0" ""
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set_parameter_property FAST_VER "VISIBLE" true
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set_parameter_property FAST_VER "DISPLAY_NAME" "Enhanced transaction master"
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set_parameter_property FAST_VER "DESCRIPTION" "Increase transaction master throughput"
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set_parameter_property FAST_VER "DISPLAY_HINT" "boolean"
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set_parameter_property FAST_VER "STATUS" experimental
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add_parameter FIFO_DEPTHS "INTEGER" "2" ""
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set_parameter_property FIFO_DEPTHS "VISIBLE" true
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set_parameter_property FIFO_DEPTHS "HDL_PARAMETER" true
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set_parameter_property FIFO_DEPTHS "ALLOWED_RANGES" "2:8192"
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set_parameter_property FIFO_DEPTHS "DISPLAY_NAME" "FIFO depth"
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set_parameter_property FIFO_DEPTHS "DESCRIPTION" "User need to tweak this to find the sweet spot"
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set_parameter_property FIFO_DEPTHS "STATUS" experimental
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add_parameter USE_MEMORY_BLOCKS INTEGER 0
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set_parameter_property USE_MEMORY_BLOCKS DISPLAY_NAME "Use memory blocks instead of LEs"
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set_parameter_property USE_MEMORY_BLOCKS DISPLAY_HINT boolean
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set_parameter_property USE_MEMORY_BLOCKS UNITS None
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set_parameter_property USE_MEMORY_BLOCKS HDL_PARAMETER true
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | Validate
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# |
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proc validate {} {
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set use_pli [ get_parameter_value USE_PLI ]
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set use_fast [ get_parameter_value FAST_VER ]
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if {$use_pli == ""} {
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set_parameter_value USE_PLI 0
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set use_pli 0
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}
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if {$use_fast == ""} {
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set_parameter_value FAST_VER 0
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set use_fast 0
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}
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if {$use_pli == 0} {
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set_parameter_property PLI_PORT ENABLED false
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} else {
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set_parameter_property PLI_PORT ENABLED true
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}
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if {$use_fast == 0} {
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set_parameter_property FIFO_DEPTHS ENABLED false
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} else {
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set_parameter_property FIFO_DEPTHS ENABLED true
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}
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}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | Compose
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# |
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proc compose {} {
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# +-----------------------------------
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# | submodule instantiation
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# |
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#add_instance clk_src clock_source
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add_instance clk_src altera_clock_bridge
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add_instance clk_rst altera_reset_bridge
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add_instance jtag_phy_embedded_in_jtag_master altera_jtag_dc_streaming
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add_instance timing_adt timing_adapter
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add_instance fifo altera_avalon_sc_fifo
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add_instance b2p altera_avalon_st_bytes_to_packets
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add_instance p2b altera_avalon_st_packets_to_bytes
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add_instance transacto altera_avalon_packets_to_master
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add_instance b2p_adapter channel_adapter
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add_instance p2b_adapter channel_adapter
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# altera_reset_bridge parameters
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set_instance_parameter clk_rst SYNCHRONOUS_EDGES none
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# altera_jtag_dc_streaming parameters
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set_instance_parameter jtag_phy_embedded_in_jtag_master PURPOSE 1
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set_instance_parameter jtag_phy_embedded_in_jtag_master DOWNSTREAM_FIFO_SIZE 64
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set_instance_parameter jtag_phy_embedded_in_jtag_master USE_PLI [ get_parameter_value USE_PLI ]
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set_instance_parameter jtag_phy_embedded_in_jtag_master PLI_PORT [ get_parameter_value PLI_PORT ]
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# timing adapter parameters
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set_instance_parameter timing_adt inBitsPerSymbol 8
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set_instance_parameter timing_adt inChannelWidth 0
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set_instance_parameter timing_adt inErrorWidth 0
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set_instance_parameter timing_adt inMaxChannel 0
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set_instance_parameter timing_adt inReadyLatency 0
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set_instance_parameter timing_adt inSymbolsPerBeat 1
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set_instance_parameter timing_adt inUseEmpty false
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set_instance_parameter timing_adt inUseEmptyPort NO
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set_instance_parameter timing_adt inUsePackets false
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set_instance_parameter timing_adt inUseReady [ get_parameter_value USE_PLI ]
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set_instance_parameter timing_adt inUseValid true
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set_instance_parameter timing_adt outReadyLatency 0
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set_instance_parameter timing_adt outUseReady true
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set_instance_parameter timing_adt outUseValid true
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# b2p channel adapter parameters
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set_instance_parameter b2p_adapter inBitsPerSymbol 8
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set_instance_parameter b2p_adapter inChannelWidth 8
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set_instance_parameter b2p_adapter inErrorWidth 0
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set_instance_parameter b2p_adapter inMaxChannel 255
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set_instance_parameter b2p_adapter inReadyLatency 0
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set_instance_parameter b2p_adapter inSymbolsPerBeat 1
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set_instance_parameter b2p_adapter inUseEmpty false
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set_instance_parameter b2p_adapter inUseEmptyPort AUTO
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set_instance_parameter b2p_adapter inUsePackets true
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set_instance_parameter b2p_adapter inUseReady true
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set_instance_parameter b2p_adapter outChannelWidth 0
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set_instance_parameter b2p_adapter outMaxChannel 0
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# p2b channel adapter parameters
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set_instance_parameter p2b_adapter inBitsPerSymbol 8
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set_instance_parameter p2b_adapter inChannelWidth 0
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set_instance_parameter p2b_adapter inErrorWidth 0
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set_instance_parameter p2b_adapter inMaxChannel 0
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set_instance_parameter p2b_adapter inReadyLatency 0
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set_instance_parameter p2b_adapter inSymbolsPerBeat 1
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set_instance_parameter p2b_adapter inUseEmpty false
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set_instance_parameter p2b_adapter inUseEmptyPort AUTO
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set_instance_parameter p2b_adapter inUsePackets true
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set_instance_parameter p2b_adapter inUseReady true
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set_instance_parameter p2b_adapter outChannelWidth 8
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set_instance_parameter p2b_adapter outMaxChannel 255
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# sc fifo parameters
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set_instance_parameter fifo SYMBOLS_PER_BEAT 1
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set_instance_parameter fifo BITS_PER_SYMBOL 8
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set_instance_parameter fifo FIFO_DEPTH 64
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set_instance_parameter fifo CHANNEL_WIDTH 0
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set_instance_parameter fifo ERROR_WIDTH 0
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set_instance_parameter fifo USE_PACKETS 0
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set_instance_parameter fifo USE_FILL_LEVEL 0
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set_instance_parameter fifo USE_STORE_FORWARD 0
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set_instance_parameter fifo USE_ALMOST_FULL_IF 0
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set_instance_parameter fifo USE_ALMOST_EMPTY_IF 0
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set_instance_parameter fifo USE_MEMORY_BLOCKS [ get_parameter_value USE_MEMORY_BLOCKS ]
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# transacto parameters
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set_instance_parameter transacto EXPORT_MASTER_SIGNALS 0
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set_instance_parameter transacto FAST_VER [ get_parameter_value FAST_VER ]
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set_instance_parameter transacto FIFO_DEPTHS [ get_parameter_value FIFO_DEPTHS ]
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point clk
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# |
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add_interface clk clock end
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set_interface_property clk export_of clk_src.in_clk
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point clk_reset
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# |
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add_interface clk_reset reset end
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set_interface_property clk_reset export_of clk_rst.in_reset
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point master
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# |
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add_interface master avalon start
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set_interface_property master export_of transacto.avalon_master
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set_interface_assignment master debug.providesServices master
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set_interface_assignment master debug.visible true
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point master_reset
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# |
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add_interface master_reset reset start
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set_interface_property master_reset export_of jtag_phy_embedded_in_jtag_master.resetrequest
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | submodule interface connections
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# |
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add_connection clk_src.out_clk jtag_phy_embedded_in_jtag_master.clock
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add_connection clk_src.out_clk timing_adt.clk
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add_connection clk_src.out_clk fifo.clk
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add_connection clk_src.out_clk b2p.clk
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add_connection clk_src.out_clk p2b.clk
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add_connection clk_src.out_clk transacto.clk
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add_connection clk_src.out_clk b2p_adapter.clk
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add_connection clk_src.out_clk p2b_adapter.clk
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add_connection clk_rst.out_reset jtag_phy_embedded_in_jtag_master.clock_reset
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add_connection clk_rst.out_reset timing_adt.reset
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add_connection clk_rst.out_reset fifo.clk_reset
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add_connection clk_rst.out_reset b2p.clk_reset
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add_connection clk_rst.out_reset p2b.clk_reset
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add_connection clk_rst.out_reset transacto.clk_reset
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add_connection clk_rst.out_reset b2p_adapter.reset
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add_connection clk_rst.out_reset p2b_adapter.reset
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add_connection jtag_phy_embedded_in_jtag_master.src timing_adt.in
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add_connection timing_adt.out fifo.in
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add_connection fifo.out b2p.in_bytes_stream
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add_connection b2p.out_packets_stream b2p_adapter.in
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add_connection b2p_adapter.out transacto.in_stream
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add_connection transacto.out_stream p2b_adapter.in
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add_connection p2b_adapter.out p2b.in_packets_stream
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add_connection p2b.out_bytes_stream jtag_phy_embedded_in_jtag_master.sink
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# |
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# +-----------------------------------
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}
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# |
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# +-----------------------------------
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## Add documentation links for user guide and/or release notes
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add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1401396548170
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2
ossc.qsf
2
ossc.qsf
@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
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set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name SEED 3
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set_global_assignment -name SEED 1
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3
sys.qsys
3
sys.qsys
@ -416,7 +416,7 @@
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</module>
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<module
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name="master_0"
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kind="altera_jtag_avalon_master"
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kind="altera_jtag_avalon_master_mod"
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version="17.1"
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enabled="1">
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<parameter name="AUTO_DEVICE" value="EP4CE15E22C8" />
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@ -427,6 +427,7 @@
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<parameter name="FIFO_DEPTHS" value="2" />
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<parameter name="PLI_PORT" value="50000" />
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<parameter name="USE_PLI" value="0" />
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<parameter name="USE_MEMORY_BLOCKS" value="0" />
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</module>
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<module
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name="onchip_memory2_0"
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18
sys.sopcinfo
18
sys.sopcinfo
@ -1,11 +1,11 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
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<!-- Format version 17.1 590 (Future versions may contain additional information.) -->
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<!-- 2019.10.03.01:49:36 -->
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<!-- 2019.10.03.23:37:09 -->
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<!-- A collection of modules and connections -->
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<parameter name="AUTO_GENERATION_ID">
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<type>java.lang.Integer</type>
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<value>1570056576</value>
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<value>1570135029</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>false</visible>
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@ -4102,7 +4102,7 @@ parameters are a RESULT of the module parameters. -->
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</module>
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<module
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name="master_0"
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kind="altera_jtag_avalon_master"
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kind="altera_jtag_avalon_master_mod"
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version="17.1"
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path="master_0">
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<!-- Describes a single module. Module parameters are
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@ -4153,6 +4153,14 @@ the requested settings for a module instance. -->
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="USE_MEMORY_BLOCKS">
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<type>int</type>
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<value>0</value>
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<derived>false</derived>
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<enabled>true</enabled>
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<visible>true</visible>
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<valid>true</valid>
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</parameter>
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<parameter name="AUTO_DEVICE_FAMILY">
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<type>java.lang.String</type>
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<value>CYCLONEIVE</value>
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@ -12605,10 +12613,10 @@ parameters are a RESULT of the module parameters. -->
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</plugin>
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<plugin>
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<instanceCount>1</instanceCount>
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<name>altera_jtag_avalon_master</name>
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<name>altera_jtag_avalon_master_mod</name>
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<type>com.altera.entityinterfaces.IElementClass</type>
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<subtype>com.altera.entityinterfaces.IModule</subtype>
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<displayName>JTAG to Avalon Master Bridge</displayName>
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<displayName>JTAG to Avalon Master Bridge (customized)</displayName>
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<version>17.1</version>
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</plugin>
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<plugin>
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