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https://github.com/marqs85/ossc.git
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correct even/odd field naming
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b22365af20
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ba4614a4f8
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@ -52,12 +52,12 @@
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`define VSYNCGEN_GENMID_BIT 0
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`define VSYNCGEN_GENMID_BIT 0
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`define VSYNCGEN_CHOPMID_BIT 1
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`define VSYNCGEN_CHOPMID_BIT 1
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`define FID_EVEN 1'b0
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`define FID_ODD 1'b0
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`define FID_ODD 1'b1
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`define FID_EVEN 1'b1
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`define MIN_VALID_LINES 256 //power of 2 optimization -> ignore lower bits with comparison
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`define MIN_VALID_LINES 256 //power of 2 optimization -> ignore lower bits with comparison
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`define DBLFRAME_THOLD 5
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`define DBLFRAME_THOLD 5
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`define FALSE_FIELD (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_ODD))
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`define FALSE_FIELD (fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] & (FID_in == `FID_EVEN))
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`define HSYNC_LEADING_EDGE ((HSYNC_in_L == `HI) & (HSYNC_in == `LO))
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`define HSYNC_LEADING_EDGE ((HSYNC_in_L == `HI) & (HSYNC_in == `LO))
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`define VSYNC_LEADING_EDGE ((VSYNC_in_L == `HI) & (VSYNC_in == `LO))
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`define VSYNC_LEADING_EDGE ((VSYNC_in_L == `HI) & (VSYNC_in == `LO))
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@ -745,8 +745,8 @@ assign h_unstable = (warn_h_unstable != 0);
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assign pll_lock_lost = (warn_pll_lock_lost != 0);
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assign pll_lock_lost = (warn_pll_lock_lost != 0);
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//Detect if TVP7002 is skipping VSYNCs. This occurs for interlaced signals fed via digital sync inputs,
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//Detect if TVP7002 is skipping VSYNCs. This occurs for interlaced signals fed via digital sync inputs,
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//causing TVP7002 not to regenerate VSYNC for field 1. Moreover, if leading edges of HSYNC and VSYNC are
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//causing TVP7002 not to regenerate VSYNC for even field. Moreover, if leading edges of HSYNC and VSYNC are
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//too far from each other for field 0, no VSYNC is regenerated at all. This can be avoided by disabling
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//too far from each other for odd field, no VSYNC is regenerated at all. This can be avoided by disabling
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//doubled sampling rates ("AV3 interlacefix") and/or minimizing VSYNC delay induced by RC filter on PCB.
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//doubled sampling rates ("AV3 interlacefix") and/or minimizing VSYNC delay induced by RC filter on PCB.
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//However, TVP7002 datasheet warns that HSYNC/VSYNC should not change simultaneously, so leaving out the
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//However, TVP7002 datasheet warns that HSYNC/VSYNC should not change simultaneously, so leaving out the
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//filter may lead to stability issues and is not recommended. A combination of 220ohm resistor and 1nF
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//filter may lead to stability issues and is not recommended. A combination of 220ohm resistor and 1nF
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@ -846,8 +846,8 @@ begin
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end
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end
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if (`HSYNC_LEADING_EDGE) begin
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if (`HSYNC_LEADING_EDGE) begin
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if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or even field (interlace) start
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if (`VSYNC_LEADING_EDGE) begin // non-interlace frame or odd field (interlace) start
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FID_cur <= 1'b0;
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FID_cur <= `FID_ODD;
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FID_last <= FID_cur;
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FID_last <= FID_cur;
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vcnt_1x <= 0;
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vcnt_1x <= 0;
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frame_change <= 1'b1;
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frame_change <= 1'b1;
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@ -858,9 +858,9 @@ begin
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vcnt_1x <= vcnt_1x + 1'b1;
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vcnt_1x <= vcnt_1x + 1'b1;
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vcnt_tvp <= vcnt_tvp + 1'b1;
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vcnt_tvp <= vcnt_tvp + 1'b1;
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end
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end
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end else if (`VSYNC_LEADING_EDGE) begin // odd field (interlace) start
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end else if (`VSYNC_LEADING_EDGE) begin // even field (interlace) start
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if (!`FALSE_FIELD) begin
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if (!`FALSE_FIELD) begin
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FID_cur <= 1'b1;
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FID_cur <= `FID_EVEN;
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FID_last <= FID_cur;
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FID_last <= FID_cur;
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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frame_change <= 1'b1;
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frame_change <= 1'b1;
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@ -869,7 +869,7 @@ begin
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vcnt_tvp <= 0;
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vcnt_tvp <= 0;
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vmax_tvp <= vcnt_tvp;
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vmax_tvp <= vcnt_tvp;
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end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1
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end else if ((fpga_vsyncgen[`VSYNCGEN_GENMID_BIT]) && (vcnt_tvp == (vmax_tvp>>1)) && (hcnt_1x == (hmax[~line_idx]>>1))) begin //VSM=1
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FID_cur <= 1'b1;
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FID_cur <= `FID_EVEN;
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FID_last <= FID_cur;
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FID_last <= FID_cur;
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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vcnt_1x <= 11'h7ff; // -1 for 11 bit word
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frame_change <= 1'b1;
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frame_change <= 1'b1;
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@ -879,11 +879,11 @@ begin
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if (`VSYNC_LEADING_EDGE) begin
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if (`VSYNC_LEADING_EDGE) begin
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FID_prev <= FID_in;
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FID_prev <= FID_in;
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// detect non-interlaced signal with odd-odd field signaling (TVP7002 detects it as interlaced with analog sync inputs).
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// detect non-interlaced signal with consecutive even field signaling (TVP7002 detects it as interlaced with analog sync inputs).
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// FID is updated at leading edge of VSYNC
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// FID is updated at leading edge of VSYNC
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if (FID_in == FID_prev)
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if (FID_in == FID_prev)
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fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE;
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fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= `FALSE;
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else if (FID_in == `FID_ODD) // TVP7002 falsely indicates field change with (vcnt < active_lines)
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else if (FID_in == `FID_EVEN) // TVP7002 falsely indicates field change with (vcnt < active_lines)
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fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_tvp < `MIN_VALID_LINES);
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fpga_vsyncgen[`VSYNCGEN_CHOPMID_BIT] <= (vcnt_tvp < `MIN_VALID_LINES);
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end
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end
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@ -987,7 +987,7 @@ begin
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G_1x <= G_in_LLL;
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G_1x <= G_in_LLL;
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B_1x <= B_in_LLL;
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B_1x <= B_in_LLL;
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HSYNC_1x <= (hcnt_1x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
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HSYNC_1x <= (hcnt_1x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
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if (FID_cur == `FID_EVEN)
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if (FID_cur == `FID_ODD)
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VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
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VSYNC_1x <= (vcnt_1x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
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else
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else
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VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL;
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VSYNC_1x <= (((vcnt_1x+1'b1) < V_SYNCLEN) | ((vcnt_1x+1'b1 == V_SYNCLEN) & (hcnt_1x <= (hmax[~line_idx]>>1)))) ? `VSYNC_POL : ~`VSYNC_POL;
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@ -1011,14 +1011,14 @@ begin
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line_out_idx_2x <= 0;
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line_out_idx_2x <= 0;
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if (frame_change)
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if (frame_change)
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vcnt_2x <= 11'h7ff; // -1 for 11 bit word
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vcnt_2x <= 11'h7ff; // -1 for 11 bit word
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else if (line_change & (FID_cur == `FID_EVEN))
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else if (line_change & (FID_cur == `FID_ODD))
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vcnt_2x <= vcnt_2x + 1'b1;
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vcnt_2x <= vcnt_2x + 1'b1;
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end else if (hcnt_2x == hmax[~line_idx]) begin
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end else if (hcnt_2x == hmax[~line_idx]) begin
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hcnt_2x <= 0;
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hcnt_2x <= 0;
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line_out_idx_2x <= line_out_idx_2x + 1'b1;
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line_out_idx_2x <= line_out_idx_2x + 1'b1;
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hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
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hcnt_2x_opt <= H_OPT_SAMPLE_SEL;
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hcnt_2x_opt_ctr <= 0;
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hcnt_2x_opt_ctr <= 0;
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if (FID_cur == `FID_ODD)
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if (FID_cur == `FID_EVEN)
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vcnt_2x <= vcnt_2x + 1'b1;
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vcnt_2x <= vcnt_2x + 1'b1;
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end else begin
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end else begin
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hcnt_2x <= hcnt_2x + 1'b1;
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hcnt_2x <= hcnt_2x + 1'b1;
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@ -1045,7 +1045,7 @@ begin
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line_out_idx_3x <= 0;
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line_out_idx_3x <= 0;
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end else begin
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end else begin
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if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
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if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
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if (!(frame_change & (FID_cur == `FID_ODD))) begin
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if (!(frame_change & (FID_cur == `FID_EVEN))) begin
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hcnt_3x <= 0;
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hcnt_3x <= 0;
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hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
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hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
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hcnt_3x_opt_ctr <= 0;
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hcnt_3x_opt_ctr <= 0;
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@ -1080,7 +1080,7 @@ begin
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pclk_1x_prev3x <= pclk_1x;
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pclk_1x_prev3x <= pclk_1x;
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HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
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HSYNC_3x <= (hcnt_3x < H_SYNCLEN) ? `HSYNC_POL : ~`HSYNC_POL;
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if (FID_cur == `FID_EVEN)
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if (FID_cur == `FID_ODD)
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VSYNC_3x <= (vcnt_3x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
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VSYNC_3x <= (vcnt_3x < V_SYNCLEN) ? `VSYNC_POL : ~`VSYNC_POL;
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else begin
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else begin
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if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1))
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if ((vcnt_3x+1'b1 == 11'd0) & (line_out_idx_3x == 1) & (hcnt_3x == (hmax[~line_idx]>>1)+1'b1))
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@ -1116,14 +1116,14 @@ begin
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line_out_idx_4x <= 0;
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line_out_idx_4x <= 0;
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if (frame_change)
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if (frame_change)
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vcnt_4x <= 11'h7ff; // -1 for 11 bit word
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vcnt_4x <= 11'h7ff; // -1 for 11 bit word
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else if (line_change & (FID_cur == `FID_EVEN))
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else if (line_change & (FID_cur == `FID_ODD))
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vcnt_4x <= vcnt_4x + 1'b1;
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vcnt_4x <= vcnt_4x + 1'b1;
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end else if (hcnt_4x == hmax[~line_idx]) begin
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end else if (hcnt_4x == hmax[~line_idx]) begin
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hcnt_4x <= 0;
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hcnt_4x <= 0;
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line_out_idx_4x <= line_out_idx_4x + 1'b1;
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line_out_idx_4x <= line_out_idx_4x + 1'b1;
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hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
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hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
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hcnt_4x_opt_ctr <= 0;
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hcnt_4x_opt_ctr <= 0;
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if ((FID_cur == `FID_ODD) && (line_out_idx_4x == 1))
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if ((FID_cur == `FID_EVEN) && (line_out_idx_4x == 1))
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vcnt_4x <= vcnt_4x + 1'b1;
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vcnt_4x <= vcnt_4x + 1'b1;
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end else begin
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end else begin
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hcnt_4x <= hcnt_4x + 1'b1;
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hcnt_4x <= hcnt_4x + 1'b1;
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