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* Fix mask placement and make its brightness adjustable
* Line4x
This commit is contained in:
marqs 2017-01-24 00:18:15 +02:00
parent 434186d64e
commit d41c7522a0
10 changed files with 1152 additions and 1062 deletions
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19
ossc.sdc
View File

@ -13,18 +13,12 @@ create_clock -period 108MHz -name pclk_hdtv [get_ports PCLK_in]
create_clock -period 27MHz -name pclk_ldtv_hs_M0 [get_ports PCLK_in] -add
create_clock -period 20MHz -name pclk_ldtv_hs_M1 [get_ports PCLK_in] -add
create_clock -period 13.5MHz -name pclk_sdtv [get_ports PCLK_in] -add
create_clock -period 6.7MHz -name pclk_ldtv_M2 [get_ports PCLK_in] -add
create_clock -period 5.4MHz -name pclk_ldtv_M3 [get_ports PCLK_in] -add
#derive_pll_clocks
create_generated_clock -master_clock pclk_sdtv -source {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name pclk_2x {scanconverter_inst|pll_linedouble|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_ldtv_hs_M0 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M0 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[0]} -add
create_generated_clock -master_clock pclk_ldtv_hs_M1 -source {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 4 -duty_cycle 50.00 -name pclk_4x_M1 {scanconverter_inst|pll_linetriple|altpll_component|auto_generated|pll1|clk[1]}
create_generated_clock -master_clock pclk_ldtv_M2 -source {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_h1x_M2 {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|clk[0]}
create_generated_clock -master_clock pclk_ldtv_M2 -source {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 12 -duty_cycle 50.00 -name pclk_3x_h4x_M2 {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|clk[1]}
create_generated_clock -master_clock pclk_ldtv_M3 -source {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name pclk_3x_h1x_M3 {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|clk[0]} -add
create_generated_clock -master_clock pclk_ldtv_M3 -source {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 15 -duty_cycle 50.00 -name pclk_3x_h5x_M3 {scanconverter_inst|pll_linetriple_lowfreq|altpll_component|auto_generated|pll1|clk[2]}
derive_clock_uncertainty
@ -34,10 +28,6 @@ set_input_delay -clock pclk_sdtv -min 0 $critinputs
set_input_delay -clock pclk_sdtv -max 1.5 $critinputs
set_input_delay -clock pclk_hdtv -min 0 $critinputs -add_delay
set_input_delay -clock pclk_hdtv -max 1.5 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_M2 -min 0 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_M2 -max 1.5 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_M3 -min 0 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_M3 -max 1.5 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_hs_M0 -min 0 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_hs_M0 -max 1.5 $critinputs -add_delay
set_input_delay -clock pclk_ldtv_hs_M1 -min 0 $critinputs -add_delay
@ -49,8 +39,6 @@ set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_hdtv 0 $critoutputs_hdm
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_2x 0 $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_M0 0 $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_4x_M1 0 $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_h4x_M2 0 $critoutputs_hdmi -add_delay
set_output_delay -reference_pin HDMI_TX_PCLK -clock pclk_3x_h5x_M3 0 $critoutputs_hdmi -add_delay
set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
@ -61,9 +49,7 @@ set_clock_groups -exclusive \
-group {pclk_hdtv} \
-group {pclk_sdtv pclk_2x} \
-group {pclk_ldtv_hs_M0 pclk_3x_M0} \
-group {pclk_ldtv_hs_M1 pclk_3x_M1 pclk_4x_M1} \
-group {pclk_ldtv_M2 pclk_3x_h1x_M2 pclk_3x_h4x_M2} \
-group {pclk_ldtv_M3 pclk_3x_h1x_M3 pclk_3x_h5x_M3}
-group {pclk_ldtv_hs_M1 pclk_3x_M1 pclk_4x_M1}
# Treat CPU clock asynchronous to pixel clocks
set_clock_groups -asynchronous -group {clk27}
@ -88,9 +74,6 @@ set_false_path -to [get_cells {scanconverter:scanconverter_inst|line_out_idx*}]
set_false_path -from [get_clocks pclk_2x] -to [get_clocks pclk_sdtv]
set_false_path -from [get_clocks pclk_3x_M*] -to [get_clocks {pclk_ldtv_hs_M*}]
set_false_path -from [get_clocks pclk_4x_M1] -to [get_clocks {pclk_ldtv_hs_M1 pclk_3x_M1}]
set_false_path -from [get_clocks pclk_3x_h4x_M2] -to [get_clocks {pclk_ldtv_M2 pclk_3x_h1x_M2}]
set_false_path -from [get_clocks pclk_3x_h5x_M3] -to [get_clocks {pclk_ldtv_M3 pclk_3x_h1x_M3}]
set_false_path -from [get_clocks pclk_3x_h1x_M*] -to [get_clocks {pclk_ldtv_M*}]
### JTAG Signal Constraints ###

8
rtl/ossc.v
View File

@ -57,9 +57,7 @@ wire [7:0] sys_ctrl;
wire h_unstable;
wire [2:0] pclk_lock;
wire [2:0] pll_lock_lost;
wire [31:0] h_info;
wire [31:0] hscale_info;
wire [31:0] v_info;
wire [31:0] h_info, h_info2, v_info;
wire [10:0] lines_out;
wire [1:0] fpga_vsyncgen;
@ -200,7 +198,7 @@ sys sys_inst(
.pio_2_horizontal_info_out_export (h_info),
.pio_3_vertical_info_out_export (v_info),
.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out}),
.pio_5_hscale_info_out_export (hscale_info),
.pio_5_horizontal_info2_out_export (h_info2),
);
scanconverter scanconverter_inst (
@ -213,8 +211,8 @@ scanconverter scanconverter_inst (
.G_in (G_in_L),
.B_in (B_in_L),
.h_info (h_info),
.h_info2 (h_info2),
.v_info (v_info),
.hscale_info (hscale_info),
.R_out (R_out),
.G_out (G_out),
.B_out (B_out),

155
rtl/scanconverter.v
View File

@ -63,8 +63,8 @@ module scanconverter (
input HSYNC_in,
input PCLK_in,
input [31:0] h_info,
input [31:0] h_info2,
input [31:0] v_info,
input [31:0] hscale_info,
output reg [7:0] R_out,
output reg [7:0] G_out,
output reg [7:0] B_out,
@ -88,7 +88,7 @@ wire [1:0] slid_act;
wire pclk_2x_lock, pclk_3x_lock;
wire HSYNC_act, VSYNC_act;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_pp1;
reg HSYNC_1x, HSYNC_2x, HSYNC_3x, HSYNC_4x, HSYNC_pp1;
reg VSYNC_1x, VSYNC_2x, VSYNC_pp1;
reg [11:0] HSYNC_start;
@ -100,28 +100,33 @@ reg DATA_enable_pp1;
wire [11:0] linebuf_hoffset; //Offset for line (max. 2047 pixels), MSB indicates which line is read/written
wire [11:0] hcnt_act;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_3x_opt;
reg [11:0] hcnt_1x, hcnt_2x, hcnt_3x, hcnt_4x, hcnt_4x_aspfix, hcnt_3x_opt, hcnt_4x_opt;
reg [2:0] hcnt_3x_opt_ctr;
reg [2:0] hcnt_3x_opt_ctr, hcnt_4x_opt_ctr;
wire [10:0] vcnt_act;
reg [10:0] vcnt_1x, vcnt_1x_tvp, vcnt_2x, lines_1x, lines_2x; //max. 2047
reg [9:0] vcnt_3x, vcnt_3x_h1x, lines_3x; //max. 1023
reg [9:0] vcnt_3x, lines_3x; //max. 1023
reg [10:0] vcnt_4x, lines_4x; //max. 2047
reg h_enable_3x_prev4x;
reg pclk_1x_prev3x;
reg [1:0] pclk_3x_cnt;
reg pclk_1x_prev4x;
reg [1:0] pclk_4x_cnt;
// Data enable
reg h_enable_1x, v_enable_1x;
reg h_enable_2x, v_enable_2x;
reg h_enable_3x, v_enable_3x;
reg h_enable_4x, v_enable_4x;
reg prev_hs, prev_vs;
reg [11:0] hmax[0:1];
reg line_idx;
reg [1:0] line_out_idx_2x, line_out_idx_3x;
reg [1:0] line_out_idx_2x, line_out_idx_3x, line_out_idx_4x;
reg [23:0] warn_h_unstable, warn_pll_lock_lost, warn_pll_lock_lost_3x;
@ -135,7 +140,8 @@ reg [7:0] H_SCANLINESTR;
reg [5:0] V_MASK;
reg [2:0] V_MULTMODE;
reg [1:0] H_MULTMODE;
reg [5:0] H_MASK;
reg [9:0] H_MASK;
reg [3:0] H_MASK_BR;
reg [9:0] H_OPT_STARTOFF;
reg [2:0] H_OPT_SCALE;
reg [2:0] H_OPT_SAMPLE_MULT;
@ -182,7 +188,7 @@ function [7:0] apply_mask;
input [10:0] vend;
begin
if (enable & ((hoffset < hstart) | (hoffset >= hend) | (voffset < vstart) | (voffset >= vend)))
apply_mask = 8'h00;
apply_mask = {2'h0, H_MASK_BR, 2'h0};
else
apply_mask = data;
//apply_mask = (hoffset[0] ^ voffset[0]) ? 8'b11111111 : 8'b00000000;
@ -258,9 +264,9 @@ begin
`H_MULTMODE_ASPECTFIX: begin
PCLK_out = pclk_4x;
linebuf_rdclock = pclk_4x;
linebuf_hoffset = hcnt_4x;
linebuf_hoffset = hcnt_4x_aspfix;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x;
hcnt_act = hcnt_4x_aspfix;
end
`H_MULTMODE_OPTIMIZED: begin
PCLK_out = pclk_3x;
@ -278,6 +284,32 @@ begin
end
endcase
end
`V_MULTMODE_4X: begin
R_act = R_lbuf;
G_act = G_lbuf;
B_act = B_lbuf;
HSYNC_act = HSYNC_4x;
VSYNC_act = VSYNC_1x;
DATA_enable_act = (h_enable_4x & v_enable_4x);
lines_out = lines_4x;
slid_act = line_out_idx_4x;
vcnt_act = vcnt_4x/4;
PCLK_out = pclk_4x;
linebuf_rdclock = pclk_4x;
pclk_act = pclk_4x;
hcnt_act = hcnt_4x;
case (H_MULTMODE)
`H_MULTMODE_FULLWIDTH: begin
linebuf_hoffset = hcnt_4x;
end
`H_MULTMODE_OPTIMIZED: begin
linebuf_hoffset = hcnt_4x_opt;
end
default: begin
linebuf_hoffset = hcnt_4x;
end
endcase
end
default: begin
R_act = R_1x;
G_act = G_1x;
@ -305,7 +337,7 @@ pll_2x pll_linedouble (
);
pll_3x pll_linetriple (
.areset ( (V_MULTMODE != `V_MULTMODE_3X) ),
.areset ( (V_MULTMODE != `V_MULTMODE_3X) & (V_MULTMODE != `V_MULTMODE_4X) ),
.inclk0 ( PCLK_in ),
.c0 ( pclk_3x ), // sampling clock for 240p: 1280 or 960 samples & MODE0: 1280 output pixels from 1280 input samples (16:9)
.c1 ( pclk_4x ), // MODE1: 1280 output pixels from 960 input samples (960 drawn -> 4:3 aspect)
@ -339,7 +371,7 @@ begin
begin
R_pp1 <= 8'h00;
G_pp1 <= 8'h00;
G_pp1 <= 8'h00;
B_pp1 <= 8'h00;
HSYNC_pp1 <= 1'b0;
VSYNC_pp1 <= 1'b0;
DATA_enable_pp1 <= 1'b0;
@ -352,16 +384,16 @@ begin
end
else
begin
R_pp1 <= apply_mask(1, R_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
G_pp1 <= apply_mask(1, G_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
B_pp1 <= apply_mask(1, B_act, hcnt_act, H_BACKPORCH+H_MASK, H_BACKPORCH+H_ACTIVE-H_MASK, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
R_pp1 <= apply_scanlines(V_SCANLINEMODE, R_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
G_pp1 <= apply_scanlines(V_SCANLINEMODE, G_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
B_pp1 <= apply_scanlines(V_SCANLINEMODE, B_act, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
HSYNC_pp1 <= HSYNC_act;
VSYNC_pp1 <= VSYNC_act;
DATA_enable_pp1 <= DATA_enable_act;
R_out <= apply_scanlines(V_SCANLINEMODE, R_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
G_out <= apply_scanlines(V_SCANLINEMODE, G_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
B_out <= apply_scanlines(V_SCANLINEMODE, B_pp1, H_SCANLINESTR, V_SCANLINEID, slid_act, hcnt_act[0], FID_1x);
R_out <= apply_mask(1, R_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
G_out <= apply_mask(1, G_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
B_out <= apply_mask(1, B_pp1, hcnt_act, H_BACKPORCH+H_MASK+2'h2, H_BACKPORCH+H_ACTIVE-H_MASK+2'h2, vcnt_act, V_BACKPORCH+V_MASK, V_BACKPORCH+V_ACTIVE-V_MASK);
HSYNC_out <= HSYNC_pp1;
VSYNC_out <= VSYNC_pp1;
DATA_enable <= DATA_enable_pp1;
@ -428,6 +460,7 @@ begin
H_OPT_SAMPLE_MULT <= 0;
H_OPT_SAMPLE_SEL <= 0;
H_OPT_SCALE <= 0;
H_MASK_BR <= 0;
prev_hs <= 0;
prev_vs <= 0;
HSYNC_start <= 0;
@ -475,24 +508,25 @@ begin
end
//Read configuration data from CPU
H_MULTMODE <= h_info[27:26]; // Horizontal scaling mode
H_MULTMODE <= h_info[31:30]; // Horizontal scaling mode
V_MULTMODE <= v_info[26:24]; // Line multiply mode
H_ACTIVE <= h_info[19:9]; // Horizontal active length from by the CPU - 11bits (0...2047)
H_BACKPORCH <= h_info[7:0]; // Horizontal backporch length from by the CPU - 8bits (0...255)
H_MASK <= h_info[25:20];
H_MASK <= h_info[29:20];
V_ACTIVE <= v_info[17:7]; // Vertical active length from by the CPU, 11bits (0...2047)
V_BACKPORCH <= v_info[5:0]; // Vertical backporch length from by the CPU, 6bits (0...64)
V_MASK <= v_info[23:18];
H_SCANLINESTR <= ((h_info[31:28]+8'h01)<<4)-1'b1;
H_SCANLINESTR <= ((h_info2[22:19]+8'h01)<<4)-1'b1;
V_SCANLINEMODE <= v_info[31:30];
V_SCANLINEID <= v_info[29:28];
H_OPT_STARTOFF <= hscale_info[9:0];
H_OPT_SAMPLE_MULT <= hscale_info[12:10];
H_OPT_SAMPLE_SEL <= hscale_info[15:13];
H_OPT_SCALE <= hscale_info[18:16];
H_OPT_STARTOFF <= h_info2[9:0];
H_OPT_SAMPLE_MULT <= h_info2[12:10];
H_OPT_SAMPLE_SEL <= h_info2[15:13];
H_OPT_SCALE <= h_info2[18:16];
H_MASK_BR <= h_info2[26:23];
end
prev_hs <= HSYNC_in;
@ -659,18 +693,81 @@ always @(posedge pclk_4x or negedge reset_n)
begin
if (!reset_n)
begin
hcnt_4x <= 0;
hcnt_4x_aspfix <= 0;
h_enable_3x_prev4x <= 0;
hcnt_4x <= 0;
vcnt_4x <= 0;
lines_4x <= 0;
HSYNC_4x <= 0;
h_enable_4x <= 0;
v_enable_4x <= 0;
pclk_4x_cnt <= 0;
pclk_1x_prev4x <= 0;
line_out_idx_4x <= 0;
hcnt_4x_opt <= 0;
hcnt_4x_opt_ctr <= 0;
end
else
begin
// Can we sync reliably to h_enable_3x???
if ((h_enable_3x == 1) & (h_enable_3x_prev4x == 0))
hcnt_4x <= hcnt_3x - 160;
hcnt_4x_aspfix <= hcnt_3x - 160;
else
hcnt_4x <= hcnt_4x + 1'b1;
hcnt_4x_aspfix <= hcnt_4x_aspfix + 1'b1;
h_enable_3x_prev4x <= h_enable_3x;
if ((pclk_4x_cnt == 0) & `HSYNC_TRAILING_EDGE) //sync with posedge of pclk_1x
begin
hcnt_4x <= 0;
line_out_idx_4x <= 0;
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
hcnt_4x_opt_ctr <= 0;
end
else if (hcnt_4x == hmax[~line_idx]) //line_idx_prev?
begin
hcnt_4x <= 0;
line_out_idx_4x <= line_out_idx_4x + 1'b1;
hcnt_4x_opt <= H_OPT_SAMPLE_SEL;
hcnt_4x_opt_ctr <= 0;
end
else
begin
hcnt_4x <= hcnt_4x + 1'b1;
if (hcnt_4x >= H_OPT_STARTOFF)
begin
if (hcnt_4x_opt_ctr == H_OPT_SCALE-1'b1)
begin
hcnt_4x_opt <= hcnt_4x_opt + H_OPT_SAMPLE_MULT;
hcnt_4x_opt_ctr <= 0;
end
else
hcnt_4x_opt_ctr <= hcnt_4x_opt_ctr + 1'b1;
end
end
if (hcnt_4x == 0)
vcnt_4x <= vcnt_4x + 1'b1;
if ((pclk_4x_cnt == 0) & `VSYNC_TRAILING_EDGE & !(`FALSE_FIELD)) //sync with posedge of pclk_1x
begin
vcnt_4x <= 0;
lines_4x <= vcnt_4x;
end
HSYNC_4x <= ~(hcnt_4x >= HSYNC_start);
//TODO: VSYNC_4x
h_enable_4x <= ((hcnt_4x >= H_BACKPORCH) & (hcnt_4x < H_BACKPORCH + H_ACTIVE));
v_enable_4x <= ((vcnt_4x >= (4*V_BACKPORCH)) & (vcnt_4x < (4*(V_BACKPORCH + V_ACTIVE))));
//read pclk_1x to examine when edges are synced (pclk_1x=1 @ 180deg & pclk_1x=0 @ 270deg)
if (((pclk_1x_prev4x == 1'b1) & (pclk_1x == 1'b0)) | (pclk_4x_cnt == 2'h3))
pclk_4x_cnt <= 0;
else
pclk_4x_cnt <= pclk_4x_cnt + 1'b1;
pclk_1x_prev4x <= pclk_1x;
end
end

1986
software/sys_controller/mem_init/sys_onchip_memory2_0.hex
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File diff suppressed because it is too large Load Diff

28
software/sys_controller/ossc/av_controller.c
View File

@ -301,6 +301,7 @@ status_t get_status(tvp_input_t input, video_format format)
(tc.sl_id != cm.cc.sl_id) ||
(tc.h_mask != cm.cc.h_mask) ||
(tc.v_mask != cm.cc.v_mask) ||
(tc.mask_br != cm.cc.mask_br) ||
(tc.l3m3_hmult != cm.cc.l3m3_hmult))
status = (status < INFO_CHANGE) ? INFO_CHANGE : status;
@ -350,21 +351,22 @@ status_t get_status(tvp_input_t input, video_format format)
return status;
}
// h_info: [31:28] [27:26] [25:20] [19:9] [8] [7:0]
// | H_SCANLINESTR[3:0] | H_MULTMODE[1:0] | H_MASK[5:0] | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] |
// h_info: [31:30] [29:20] [19:9] [8] [7:0]
// | H_MULTMODE[1:0] | H_MASK[9:0] | H_ACTIVE[10:0] | | H_BACKPORCH[7:0] |
//
// h_info2: [31:27] [26:23] [22:19] [18:16] [15:13] [12:10] [9:0]
// | | H_MASK_BR[3:0] | H_SCANLINESTR[3:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
//
// v_info: [31:30] [29:28] [27] [26:24] [23:18] [17:7] [6] [5:0]
// | V_SCANLINEMODE[1:0] | V_SCANLINEID | | V_MULTMODE[2:0] | V_MASK[5:0] | V_ACTIVE[10:0] | | V_BACKPORCH[5:0] |
//
// hscale_info: [31:19] [18:16] [15:13] [12:10] [9:0]
// | | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0]
//
void set_videoinfo()
{
alt_u8 slid_target;
alt_u8 sl_mode_fpga;
alt_u8 h_opt_scale = 0;
alt_u8 h_opt_scale = 1;
alt_u16 h_opt_startoffs = 0;
alt_u16 h_border, h_mask;
if (cm.fpga_vmultmode == FPGA_V_MULTMODE_3X)
slid_target = cm.cc.sl_id ? (cm.cc.sl_type == 1 ? 1 : 2) : 0;
@ -391,17 +393,25 @@ void set_videoinfo()
case MODE_L3_256_COL:
h_opt_scale = cm.cc.l3m3_hmult;
break;
case MODE_L4_320_COL:
h_opt_scale = 4;
break;
case MODE_L4_256_COL:
h_opt_scale = 5;
break;
default:
break;
}
h_opt_startoffs = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2) + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*video_modes[cm.id].h_backporch) / cm.sample_mult);
h_border = (((cm.sample_mult-h_opt_scale)*video_modes[cm.id].h_active)/2);
h_mask = h_border + h_opt_scale*cm.cc.h_mask;
h_opt_startoffs = h_border + ((cm.sample_mult-h_opt_scale)*(cm.sample_mult*video_modes[cm.id].h_backporch) / cm.sample_mult);
h_opt_startoffs = (h_opt_startoffs/cm.sample_mult)*cm.sample_mult;
printf("h_opt_startoffs: %u\n", h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.cc.sl_str<<28) | (cm.fpga_hmultmode<<26) | (cm.cc.h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_2_BASE, (cm.fpga_hmultmode<<30) | (h_mask<<20) | ((cm.sample_mult*video_modes[cm.id].h_active)<<9) | cm.sample_mult*video_modes[cm.id].h_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (cm.cc.mask_br<<23) | (cm.cc.sl_str<<19) | (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (sl_mode_fpga<<30) | (slid_target<<28) | (cm.fpga_vmultmode<<24) | (cm.cc.v_mask<<18) | (video_modes[cm.id].v_active<<7) | video_modes[cm.id].v_backporch);
IOWR_ALTERA_AVALON_PIO_DATA(PIO_5_BASE, (h_opt_scale<<16) | (cm.sample_sel<<13) | (cm.sample_mult<<10) | h_opt_startoffs);
}
// Configure TVP7002 and scan converter logic based on the video mode

2
software/sys_controller/ossc/avconfig.h
View File

@ -25,6 +25,7 @@
#define SCANLINESTR_MAX 15
#define HV_MASK_MAX 63
#define HV_MASK_MAX_BR 15
#define VIDEO_LPF_MAX 5
#define SAMPLER_PHASE_MAX 31
#define SYNC_VTH_MAX 31
@ -52,6 +53,7 @@ typedef struct {
alt_u8 l3m3_hmult;
alt_u8 h_mask;
alt_u8 v_mask;
alt_u8 mask_br;
alt_u8 tx_mode;
alt_u8 s480p_mode;
alt_u8 sampler_phase;

6
software/sys_controller/ossc/menu.c
View File

@ -50,8 +50,7 @@ static const char *s480p_mode_desc[] = { LNG("Auto","ｼﾞﾄﾞｳ"), "DTV 480
static const char *sync_lpf_desc[] = { LNG("Off","ｵﾌ"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ﾊﾝﾖｳ 16:9"), LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
static const char *l4_mode_desc[] = { LNG("Generic 4:3","ﾊﾝﾖｳ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷ."), LNG("256x240 optim.","256x240 ｻｲﾃｷ.") };
//static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x" };
static const char *pm_240p_desc[] = { "Passthru", "Line2x", "Line3x", "Line4x" };
static const char *pm_384p_desc[] = { "Passthru", "Line2x" };
static const char *pm_480i_desc[] = { "Passthru", "Line2x" };
static const char *pm_480p_desc[] = { "Passthru", "Line2x" };
@ -81,7 +80,7 @@ MENU(menu_advtiming, P99_PROTECT({ \
MENU(menu_vinputproc, P99_PROTECT({ \
{ LNG("Video LPF","ﾋﾞﾃﾞｵ LPF"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.video_lpf, OPT_WRAP, SETTING_ITEM(video_lpf_desc) } } },
{ LNG("Video LPF","ﾋﾞﾃﾞｵ LPF"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.video_lpf, OPT_WRAP, SETTING_ITEM(video_lpf_desc) } } },
{ LNG("YPbPr in ColSpa","ｲﾛｸｳｶﾝﾆYPbPr"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.ypbpr_cs, OPT_WRAP, SETTING_ITEM(ypbpr_cs_desc) } } },
{ LNG("R/Pr offset","R/Pr ｵﾌｾｯﾄ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.r_f_off, OPT_NOWRAP, 0, 0xFF, value_disp } } },
{ LNG("G/Y offset","G/Y ｵﾌｾｯﾄ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.col.g_f_off, OPT_NOWRAP, 0, 0xFF, value_disp } } },
@ -126,6 +125,7 @@ MENU(menu_postproc, P99_PROTECT({ \
{ LNG("Scanline alignm.","ｿｳｻｾﾝﾎﾟｼﾞｼｮﾝ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.sl_id, OPT_WRAP, SETTING_ITEM(sl_id_desc) } } },
{ LNG("Horizontal mask","ｽｲﾍｲﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.h_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
{ LNG("Vertical mask","ｽｲﾁｮｸﾏｽｸ"), OPT_AVCONFIG_NUMVALUE, { .num = { &tc.v_mask, OPT_NOWRAP, 0, HV_MASK_MAX, pixels_disp } } },
{ "Mask brightness", OPT_AVCONFIG_NUMVALUE, { .num = { &tc.mask_br, OPT_NOWRAP, 0, HV_MASK_MAX_BR, value_disp } } },
}))
#ifdef DIY_AUDIO

4
software/sys_controller_bsp/settings.bsp
View File

@ -2,8 +2,8 @@
<sch:Settings xmlns:sch="http://www.altera.com/embeddedsw/bsp/schema">
<BspType>hal</BspType>
<BspVersion>default</BspVersion>
<BspGeneratedTimeStamp>Jan 23, 2017 12:33:30 AM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1485124410921</BspGeneratedUnixTimeStamp>
<BspGeneratedTimeStamp>Jan 23, 2017 11:53:50 PM</BspGeneratedTimeStamp>
<BspGeneratedUnixTimeStamp>1485208430382</BspGeneratedUnixTimeStamp>
<BspGeneratedLocation>./</BspGeneratedLocation>
<BspSettingsFile>settings.bsp</BspSettingsFile>
<SopcDesignFile>../../sys.sopcinfo</SopcDesignFile>

2
sys.qsys
View File

@ -315,7 +315,7 @@
type="conduit"
dir="end" />
<interface
name="pio_5_hscale_info_out"
name="pio_5_horizontal_info2_out"
internal="pio_5.external_connection"
type="conduit"
dir="end" />

4
sys.sopcinfo
View File

@ -1,11 +1,11 @@
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="sys" kind="sys" version="1.0" fabric="QSYS">
<!-- Format version 16.1 196 (Future versions may contain additional information.) -->
<!-- 2017.01.23.00:27:33 -->
<!-- 2017.01.23.23:51:34 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1485124053</value>
<value>1485208293</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>