4 Commits

Author	SHA1	Message	Date
marqs	9c2cdd64cf	Some codebase reordering	2016-05-25 00:04:46 +03:00
marqs	119d2fee15	Misc updates and fixes ... -add YPbPr input mode for AV1 and AV3 -utilize more remote control keys -fix sync LFP load from saved setting -add vsync threshold setting -add option to reset settings -refactor some code	2016-05-24 00:35:30 +03:00
marqs	c83653c880	Release 0.69 ... * Improved remote control handling code * Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal * Fixed randomly missing blue channel at power-on when using DVI output mode * Added H-PLL coast options * Finer tuning range for scanline strength and mask	2016-04-15 22:05:53 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00