marqs
2bac00fd82
TX improvements
...
* tweak audio parameters
* set AFE level based on PCLK
2019-01-11 00:26:40 +02:00
marqs
4676cbd2f0
integrate zero-riscy
2018-10-06 13:19:12 +03:00
marqs
9d14cc776e
Misc small fixes and improvements
...
* Disable 480p scanlines in auto mode
* Remove inoperable 3x/4x processing modes from 1080i list
* Add 640x512 mode to 480p group and limit 480p sampler option to 525-line modes
* Fix occasional pixel repetion issue after HDMI<->DVI TX switch
* Add "Allow upsample2x" option
* Add comments to some unclear sections
2017-08-10 00:06:35 +03:00
borti4938
e9fbf2a1b9
bugfix: screwed up register definitions
2017-06-04 23:24:23 +02:00
borti4938
5b5c8bc373
Update it6613_drv.c
...
lines outdated
2017-06-01 22:29:24 +02:00
borti4938
b471589ae1
Bugfix: audio down-sampling setting, clock settings
2017-06-01 21:23:22 +02:00
marqs
2577470abe
Clean up TX setup code and add compatibility options
2017-05-29 20:43:24 +03:00
marqs
4f36278cb7
Sync processing rewritten and some issues fixed
...
* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
marqs
0f8439abf3
Profile support added.
2016-12-30 00:14:12 +02:00
marqs
fac88b348e
Merge borti4938's diy-audio code and fix audio format.
2016-11-08 20:53:58 +02:00
marqs
f55e9a877e
SD SPI implementation finished
2016-10-21 01:19:53 +03:00
marqs
71d60144e8
Timer and SPI added.
2016-10-16 12:53:54 +03:00
marqs
a488422089
* Fix scanline rendering issues
...
* Add initial input and SDTV sync glitch filter settings
* Modify input initialization logic
* Fix debug build warnings
2016-08-14 18:57:50 +03:00
marqs
c8b542b917
* 480p/576p line2x
...
* 480i/576i passthrough
* alternating scanlines for interlaced material
2016-07-09 23:12:35 +03:00
marqs
6c5f753245
Misc updates
...
-optimizations from Borti
-more code refactoring
-fix build warnings
-change scanline mode logic
2016-06-12 23:43:24 +03:00
marqs
f502b2e46c
Release 0.67.
...
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
2016-03-27 23:09:31 +03:00
marqs
388c464f63
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
