8 Commits

Author	SHA1	Message	Date
marqs	353437ab87	sync processing and preset improvements ... * increase accurary of vblank region calculation * increase selectable PLL coast range * fix GBI preset H multiplication factors * enable 1250i/50 detection	2024-01-07 23:00:16 +02:00
marqs	0ce2809183	add Line6x mode for 240p/288p	2023-08-23 21:34:40 +03:00
marqs	31851f372d	restore hybrid scanlines and reverse LPF functions	2023-08-07 18:18:53 +03:00
marqs	a3a3304152	tvp7002: detect missing hsync only during vsync	2023-08-05 22:41:07 +03:00
marqs	ab6bd9fc8a	calculate hsync width on FPGA instead of reading TVP7002	2023-05-28 17:06:07 +03:00
marqs	df643ec742	improve TVP7002 frontend sync detection ... Store csync leading edge position so that field change timing can be calculated accurately upon VSYNC detection	2023-03-11 12:32:26 +02:00
marqs	a8a3142071	add sync activity detection on tvp7002 frontend	2023-02-13 18:53:20 +02:00
marqs	db1cf5922f	tvp7002 related robustness improvements ... * bypass VSYNC processing * enable raw SOG/HSYNC output * add frontend RTL to read status from unprocessed signals	2023-01-31 20:49:08 +02:00