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160 Commits 4 Branches 34 Tags 8.1 MiB
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Author SHA1 Message Date
marqs
525c08a777 fix debug mode printf 2018-10-21 00:04:46 +03:00
marqs
0905620b4d update qsys+bsp build logic and instructions 2018-10-11 00:04:32 +03:00
marqs
055a794b5e move bitswap inside epcq_controller driver 2018-10-09 23:16:37 +03:00
marqs
9777fe8e66 Merge branch 'megari-userdata_import' into rv-integration 2018-10-09 20:57:44 +03:00
Ari Sundholm
4984ecf418 Implement loading settings from SD card 2018-10-08 16:58:26 +03:00
Ari Sundholm
a5b329584e Factor writing to Flash memory and SD->Flash copying into functions 
This is in preparation for the feature to import settings from the
SD card.
 2018-10-08 16:58:26 +03:00
marqs
7914a2ee83 clean up and update README 2018-10-08 00:37:42 +03:00
marqs
e8d5097ecb replace nios crcCI with hw_crc32 qsys module 2018-10-07 23:38:26 +03:00
marqs
0a747cbce6 i2c_opencores: fix compilation warnings 2018-10-07 23:34:29 +03:00
marqs
4676cbd2f0 integrate zero-riscy 2018-10-06 13:19:12 +03:00
marqs
e1d8446752 BSP and sw modifications 2018-09-26 00:19:24 +03:00
marqs
530df663b6 add a list of contributors 2018-05-05 11:29:07 +03:00
marqs
22e49300df fix line2x reverse LPF trigger 2018-04-18 23:14:24 +03:00
marqs
c91988e5fb some desperate code size savings 2018-04-16 20:08:11 +03:00
marqs
183b0fa78f Merge branch 'paulb-nl-gain' into release 2018-04-16 19:26:05 +03:00
paulb-nl
5dd9f65bc6 Add video Pre-ADC gain setting 2018-04-16 12:21:31 +02:00
marqs
70ab55c1fa fix optimized mode mask & position offsets 2018-04-15 23:41:26 +03:00
marqs
dcd3d14a53 fix applying of power-on default settings 2018-04-13 01:24:34 +03:00
marqs
37650ca22b misc improvements 
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
 2018-03-28 20:09:40 +03:00
marqs
5422953f30 minor optimizations 2018-03-25 00:32:06 +02:00
marqs
e6e970227a Merge branch 'megari-profile_handling_simplified' into release 2018-03-24 12:40:11 +02:00
Ari Sundholm
b464a9224b Improve avoidance of profile load induced profile loads 
It was buggy anyway, as pointed out by borti4938.
 2018-03-15 13:28:37 +02:00
Ari Sundholm
0bb490faa0 Don't automagically update profile->input link 2018-03-15 13:27:12 +02:00
Ari Sundholm
5852eb3465 Prevent profile loads induced by profile loads 2018-03-15 13:27:12 +02:00
Ari Sundholm
f337852e19 Implement two-way profile linking in a minimalistic way 2018-03-15 13:27:12 +02:00
borti4938
6278e1026d some code space optimization 2018-03-12 08:05:09 +01:00
marqs
9ad696dbc3 optimize away one pp stage and unify code formatting 2018-03-12 01:25:23 +02:00
marqs
77d122940b Merge branch 'borti4938-upstream' into release 2018-03-11 22:22:43 +02:00
marqs
ba648dd5fe additional timing constraint fixes 2018-03-11 22:22:04 +02:00
borti4938
f3e9489856 remove duplicates from old structure 2018-03-10 19:58:37 +01:00
borti4938
6877faa0b6 remove _bb.v files 2018-03-10 19:26:40 +01:00
borti4938
a58255b8d1 suggested fitter seed 2018-03-07 10:21:40 +01:00
borti4938
852054cdd0 finer granulated steps for hybrid sl settings 2018-03-07 10:21:18 +01:00
borti4938
985aeb1a93 use explicite ramstyle for post-processing pipeline to keep registers in logic (as suggested in pull-request #21 comments) 2018-03-07 09:45:27 +01:00
borti4938
45ca4e9268 undo changes as suggested in pull-request #21 comments 2018-03-07 09:43:37 +01:00
borti4938
0828addc83 Merge branch 'release' of https://github.com/marqs85/ossc into upstream 2018-03-07 08:29:49 +01:00
marqs
0ab31b30b4 simplify timing constraints 2018-03-07 09:21:19 +02:00
marqs
bd1d58660c Add detection for 640x400 VGA Mode 13h 2018-03-06 23:52:10 +02:00
borti4938
d89c06b987 some fitter seeds for the current implementation 2018-03-06 14:43:49 +01:00
borti4938
5922e64f55 registered outputs to HDMI-TX after final mux 2018-03-06 13:08:47 +01:00
borti4938
209130b167 misc updates: 
- integrate mask and border generation more deeply into the post processing chain
- delay RLPF by one PP stage (reduce logic length after large mux)
- synthesise a registers after several adder logics
 2018-03-06 13:08:20 +01:00
borti4938
9ba41ec240 Alternative fitter seed for current design 2018-03-06 12:14:30 +01:00
borti4938
10eff56f28 Merge branch 'release' of https://github.com/marqs85/ossc into upstream 2018-03-06 09:41:59 +01:00
borti4938
d7ee965d89 add missing IP files 2018-03-06 09:36:38 +01:00
borti4938
670f515141 various post processing pipeline updates: 
- increase number of pipeline stages for scanline generation
- alternative hybrid strength implementation
- add missing file declaration in qsf
 2018-03-06 09:36:21 +01:00
borti4938
b10d7f3762 SL Multiplication: 
- Hybrid value based on Y (Y calculated according to YCoCg appr.)
- Use 8bit input as p-factor
 2018-03-06 09:34:12 +01:00
borti4938
3154a83847 re-rename of sl gen option 2018-03-06 09:33:57 +01:00
borti4938
ba8ad6ce4c add missing IP files 2018-03-06 09:33:28 +01:00
borti4938
0b51fd7758 - resolve conflicts from merge 
- use hybrid contrast for both sl generation methods: multiplication and linear
 2018-03-06 09:32:02 +01:00
borti4938
1a405c1e2e Merge branch 'scanline_contrast' of https://github.com/paulb-nl/ossc into upstream 
# Conflicts:
#	rtl/scanconverter.v
#	software/sys_controller/ossc/av_controller.c
 2018-03-06 09:30:22 +01:00