marqs
70ab55c1fa
fix optimized mode mask & position offsets
2018-04-15 23:41:26 +03:00
marqs
dcd3d14a53
fix applying of power-on default settings
2018-04-13 01:24:34 +03:00
marqs
37650ca22b
misc improvements
...
* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
2018-03-28 20:09:40 +03:00
marqs
5422953f30
minor optimizations
2018-03-25 00:32:06 +02:00
marqs
e6e970227a
Merge branch 'megari-profile_handling_simplified' into release
2018-03-24 12:40:11 +02:00
Ari Sundholm
b464a9224b
Improve avoidance of profile load induced profile loads
...
It was buggy anyway, as pointed out by borti4938.
2018-03-15 13:28:37 +02:00
Ari Sundholm
0bb490faa0
Don't automagically update profile->input link
2018-03-15 13:27:12 +02:00
Ari Sundholm
5852eb3465
Prevent profile loads induced by profile loads
2018-03-15 13:27:12 +02:00
Ari Sundholm
f337852e19
Implement two-way profile linking in a minimalistic way
2018-03-15 13:27:12 +02:00
borti4938
6278e1026d
some code space optimization
2018-03-12 08:05:09 +01:00
marqs
9ad696dbc3
optimize away one pp stage and unify code formatting
2018-03-12 01:25:23 +02:00
marqs
77d122940b
Merge branch 'borti4938-upstream' into release
2018-03-11 22:22:43 +02:00
marqs
ba648dd5fe
additional timing constraint fixes
2018-03-11 22:22:04 +02:00
borti4938
f3e9489856
remove duplicates from old structure
2018-03-10 19:58:37 +01:00
borti4938
6877faa0b6
remove _bb.v files
2018-03-10 19:26:40 +01:00
borti4938
a58255b8d1
suggested fitter seed
2018-03-07 10:21:40 +01:00
borti4938
852054cdd0
finer granulated steps for hybrid sl settings
2018-03-07 10:21:18 +01:00
borti4938
985aeb1a93
use explicite ramstyle for post-processing pipeline to keep registers in logic (as suggested in pull-request #21 comments)
2018-03-07 09:45:27 +01:00
borti4938
45ca4e9268
undo changes as suggested in pull-request #21 comments
2018-03-07 09:43:37 +01:00
borti4938
0828addc83
Merge branch 'release' of https://github.com/marqs85/ossc into upstream
2018-03-07 08:29:49 +01:00
marqs
0ab31b30b4
simplify timing constraints
2018-03-07 09:21:19 +02:00
marqs
bd1d58660c
Add detection for 640x400 VGA Mode 13h
2018-03-06 23:52:10 +02:00
borti4938
d89c06b987
some fitter seeds for the current implementation
2018-03-06 14:43:49 +01:00
borti4938
5922e64f55
registered outputs to HDMI-TX after final mux
2018-03-06 13:08:47 +01:00
borti4938
209130b167
misc updates:
...
- integrate mask and border generation more deeply into the post processing chain
- delay RLPF by one PP stage (reduce logic length after large mux)
- synthesise a registers after several adder logics
2018-03-06 13:08:20 +01:00
borti4938
9ba41ec240
Alternative fitter seed for current design
2018-03-06 12:14:30 +01:00
borti4938
10eff56f28
Merge branch 'release' of https://github.com/marqs85/ossc into upstream
2018-03-06 09:41:59 +01:00
borti4938
d7ee965d89
add missing IP files
2018-03-06 09:36:38 +01:00
borti4938
670f515141
various post processing pipeline updates:
...
- increase number of pipeline stages for scanline generation
- alternative hybrid strength implementation
- add missing file declaration in qsf
2018-03-06 09:36:21 +01:00
borti4938
b10d7f3762
SL Multiplication:
...
- Hybrid value based on Y (Y calculated according to YCoCg appr.)
- Use 8bit input as p-factor
2018-03-06 09:34:12 +01:00
borti4938
3154a83847
re-rename of sl gen option
2018-03-06 09:33:57 +01:00
borti4938
ba8ad6ce4c
add missing IP files
2018-03-06 09:33:28 +01:00
borti4938
0b51fd7758
- resolve conflicts from merge
...
- use hybrid contrast for both sl generation methods: multiplication and linear
2018-03-06 09:32:02 +01:00
borti4938
1a405c1e2e
Merge branch 'scanline_contrast' of https://github.com/paulb-nl/ossc into upstream
...
# Conflicts:
# rtl/scanconverter.v
# software/sys_controller/ossc/av_controller.c
2018-03-06 09:30:22 +01:00
marqs
bc1b7419f2
pcm1862: add pre-ADC gain setting
2018-03-02 23:11:52 +02:00
paulb-nl
990bc1563e
Add Scanline contrast
...
Reduce scanline strength for bright pixels
2018-02-24 21:56:18 +01:00
marqs
1cc42b808d
pcm1862: fix ADC clkdiv value and use low-latency IIR filter
2018-02-22 22:48:00 +02:00
borti4938
500a22f316
small simplification on reverse lpf implementation
2018-02-22 13:45:19 +01:00
borti4938
5249d313d8
scanlines generation via multiplication
2018-02-22 08:11:26 +01:00
marqs
9a2c9bb020
Merge branch 'paulb-nl-grayramp' into release
2018-01-26 01:07:07 +02:00
paulb-nl
a39888845a
Add 32 step grayramp to test pattern
2018-01-20 22:08:10 +01:00
marqs
bee64c6fbc
allow profile link (to each logical input) via a menu option
2017-12-11 00:51:50 +02:00
marqs
8caa4c1952
Merge branch 'megari-save_last_profile_per_input' into release
2017-12-07 23:29:51 +02:00
marqs
09c735bd5f
Merge branch 'save_last_profile_per_input' of git://github.com/megari/ossc into megari-save_last_profile_per_input
2017-12-07 23:29:36 +02:00
marqs
dd4ffde231
update to Quartus 17.1
2017-12-07 21:35:08 +02:00
Ari Sundholm
04c9137e29
Move default input field from profiles to initconfig
...
This makes things consistent. Without this change, the default
input would be dictated by the profile associated with AV1.
2017-11-11 00:45:49 +02:00
Ari Sundholm
d638b6a650
Shrink write_userdata() by 20 bytes
2017-11-11 00:25:33 +02:00
Ari Sundholm
571b588da7
Shrink the code by 16 bytes by using an array to map values
2017-11-11 00:25:33 +02:00
Ari Sundholm
ab61fd0c67
Don't save initconfig every time the physical input and profile change
...
This spares the Flash from some unnecessary writes. If the profile
tied to a physical input changes, this change will be reflected in the
initconfig when the new profile is loaded.
2017-11-11 00:25:33 +02:00
Ari Sundholm
1979bdb333
Save the last profile used for each physical input
2017-11-02 23:38:43 +02:00
