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Commit Graph

16 Commits

Author SHA1 Message Date
marqs
9f086828ac Release 0.73
* Fixed adv. timing tweaker using previous values when updating parameters
* Added "Hsync tolerance" option to fix detection of certain Neo-Geo models
2016-09-05 20:49:41 +03:00
marqs
c9012c2d84 Minor fixes 2016-08-23 19:24:22 +03:00
marqs
9f7a30bea9 fix clamp and ALC position 2016-08-23 00:52:46 +03:00
marqs
2dee0a2eb5 * R/G/B gain/offset controls added
* misc optimizations
2016-08-20 15:54:28 +03:00
marqs
827df7930f * L3 optimized mode scanlines fixed
* Advanced timing tweaker implemented
2016-08-16 22:45:23 +03:00
marqs
a488422089 * Fix scanline rendering issues
* Add initial input and SDTV sync glitch filter settings
* Modify input initialization logic
* Fix debug build warnings
2016-08-14 18:57:50 +03:00
marqs
a2e10637bd Fix random input detection issue. 2016-06-22 23:22:59 +03:00
marqs
6c5f753245 Misc updates
-optimizations from Borti
-more code refactoring
-fix build warnings
-change scanline mode logic
2016-06-12 23:43:24 +03:00
marqs
51c43a7c10 Fix linetriple aspect and parameters. 2016-06-08 21:16:58 +03:00
marqs
4548bf0b8c Reset sync processing when disabling output 2016-05-25 01:06:48 +03:00
borti4938
e8c8347496 ALC option 2016-05-24 01:11:37 +03:00
borti4938
c4bb809c3c move setting RGB gain out of tvp_set_alc(): miss leading name, gains set are not part of the Automatic Level Control (ALC) 2016-05-24 00:52:09 +03:00
marqs
119d2fee15 Misc updates and fixes
-add YPbPr input mode for AV1 and AV3
-utilize more remote control keys
-fix sync LFP load from saved setting
-add vsync threshold setting
-add option to reset settings
-refactor some code
2016-05-24 00:35:30 +03:00
marqs
c83653c880 Release 0.69
* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
2016-04-15 22:05:53 +03:00
marqs
f502b2e46c Release 0.67.
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
2016-03-27 23:09:31 +03:00
marqs
388c464f63 Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00