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mirror of https://github.com/marqs85/ossc.git synced 2024-11-19 20:30:53 +00:00
Commit Graph

15 Commits

Author SHA1 Message Date
marqs
70ab55c1fa fix optimized mode mask & position offsets 2018-04-15 23:41:26 +03:00
marqs
a0c0620022 Use native 2x sampling only if h_total is below 1400 2017-10-11 07:33:52 +03:00
marqs
9d14cc776e Misc small fixes and improvements
* Disable 480p scanlines in auto mode
* Remove inoperable 3x/4x processing modes from 1080i list
* Add 640x512 mode to 480p group and limit 480p sampler option to 525-line modes
* Fix occasional pixel repetion issue after HDMI<->DVI TX switch
* Add "Allow upsample2x" option
* Add comments to some unclear sections
2017-08-10 00:06:35 +03:00
marqs
2577470abe Clean up TX setup code and add compatibility options 2017-05-29 20:43:24 +03:00
marqs
4f36278cb7 Sync processing rewritten and some issues fixed
* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
marqs
01b5fe20ee Sync and masking improvements
* detect VSM=1 properly
* increase mask brightness
* add L2 optimized modes
* fix internal vsync alignment
2017-05-18 23:36:37 +03:00
marqs
6e043ef577 Improve input mode handling
* New options and better compatibility for Line5x
* Add support for 960i and 1080i
* Make TVP HPLL2x option user-selectable
2017-02-07 23:04:30 +02:00
marqs
3b19b2843c Preliminary Line5x implementation 2017-01-29 13:02:12 +02:00
marqs
434186d64e Improve lo-res mode processing features
* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
2017-01-23 00:56:17 +02:00
marqs
0f8439abf3 Profile support added. 2016-12-30 00:14:12 +02:00
marqs
827df7930f * L3 optimized mode scanlines fixed
* Advanced timing tweaker implemented
2016-08-16 22:45:23 +03:00
marqs
51c43a7c10 Fix linetriple aspect and parameters. 2016-06-08 21:16:58 +03:00
marqs
c83653c880 Release 0.69
* Improved remote control handling code
* Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal
* Fixed randomly missing blue channel at power-on when using DVI output mode
* Added H-PLL coast options
* Finer tuning range for scanline strength and mask
2016-04-15 22:05:53 +03:00
marqs
f502b2e46c Release 0.67.
- Code cleanup
- Some project files added
- PAL linetriple added
- FPGA PLL parameters optimized
- Reduced jitter on low video clock sources
2016-03-27 23:09:31 +03:00
marqs
388c464f63 Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00