6 Commits

Author	SHA1	Message	Date
marqs	827df7930f	* L3 optimized mode scanlines fixed ... * Advanced timing tweaker implemented	2016-08-16 22:45:23 +03:00
marqs	a488422089	* Fix scanline rendering issues ... * Add initial input and SDTV sync glitch filter settings * Modify input initialization logic * Fix debug build warnings	2016-08-14 18:57:50 +03:00
marqs	c8b542b917	* 480p/576p line2x ... * 480i/576i passthrough * alternating scanlines for interlaced material	2016-07-09 23:12:35 +03:00
marqs	c83653c880	Release 0.69 ... * Improved remote control handling code * Fixed occasional mode change loop when switching to a non-interlace mode utilizing odd-field sync signal * Fixed randomly missing blue channel at power-on when using DVI output mode * Added H-PLL coast options * Finer tuning range for scanline strength and mask	2016-04-15 22:05:53 +03:00
marqs	f502b2e46c	Release 0.67. ... - Code cleanup - Some project files added - PAL linetriple added - FPGA PLL parameters optimized - Reduced jitter on low video clock sources	2016-03-27 23:09:31 +03:00
marqs	388c464f63	Initial public release (FW 0.64)	2016-02-23 01:03:50 +02:00