9d496383c3
optimize clock network
...
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew
* use a single dynamically configured PLL to comply with cycloneive_clkctrl
2019-10-06 23:54:32 +03:00
6266976114
first OSD implementation
2019-10-03 02:03:43 +03:00
9e81fb5922
Scanline updates and fixes
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* Enable overlay pattern customization
* Fix non-alternating mode with line4x interlace sources
* Add alternate interval option for pre-linedoubled sources
2019-03-23 00:09:46 +02:00
e8d5097ecb
replace nios crcCI with hw_crc32 qsys module
2018-10-07 23:38:26 +03:00
4676cbd2f0
integrate zero-riscy
2018-10-06 13:19:12 +03:00
e1d8446752
BSP and sw modifications
2018-09-26 00:19:24 +03:00
37650ca22b
misc improvements
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* add character LCD backlight timeout option
* increase h.mask range
* show accurate (fpga-calculated) timings on infoscreen
2018-03-28 20:09:40 +03:00
a24d6b0e3a
Update latency tester
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* Enable operation with all sources
* Measure strobe length on low-persistence displays
2017-10-28 12:10:54 +03:00
1bf279b2a7
Initial latency tester implementation
2017-10-22 22:45:29 +03:00
4f36278cb7
Sync processing rewritten and some issues fixed
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* add 480i/576i line3x/4x
* clean up RTL and SDC
* update AVI infoframe properly
* add HDMI IT content option
2017-05-18 23:36:37 +03:00
434186d64e
Improve lo-res mode processing features
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* workaround for phase shift issue on optimized modes
* add hscale option for 256x240 opt Line3x mode
* distribute video modes to groups and allow passthru for all modes
2017-01-23 00:56:17 +02:00
d77c293b70
* Clean up some FPGA code
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* Wrap sampling phase setting
* Enable hal.enable_lightweight_device_driver_api to reduce CPU code size
2016-12-31 14:18:21 +02:00
f55e9a877e
SD SPI implementation finished
2016-10-21 01:19:53 +03:00
71d60144e8
Timer and SPI added.
2016-10-16 12:53:54 +03:00
388c464f63
Initial public release (FW 0.64)
2016-02-23 01:03:50 +02:00
