# -------------------------------------------------------------------------- # # # Copyright (C) 1991-2013 Altera Corporation # Your use of Altera Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Altera Program License # Subscription Agreement, Altera MegaCore Function License # Agreement, or other applicable license agreement, including, # without limitation, that your use is for the sole purpose of # programming logic devices manufactured by Altera and sold by # Altera or its authorized distributors. Please refer to the # applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus II 64-Bit # Version 13.1.0 Build 162 10/23/2013 SJ Web Edition # Date created = 17:27:03 May 17, 2014 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # ossc_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus II software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE15E22C8 set_global_assignment -name TOP_LEVEL_ENTITY ossc set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:27:03 MAY 17, 2014" set_global_assignment -name LAST_QUARTUS_VERSION "17.0.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name EDA_SIMULATION_TOOL "" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_location_assignment PIN_25 -to clk27 set_location_assignment PIN_99 -to reset_n set_location_assignment PIN_23 -to ir_rx #============================================================ # TVP7002 #============================================================ set_location_assignment PIN_52 -to R_in[0] set_location_assignment PIN_53 -to R_in[1] set_location_assignment PIN_54 -to R_in[2] set_location_assignment PIN_55 -to R_in[3] set_location_assignment PIN_58 -to R_in[4] set_location_assignment PIN_59 -to R_in[5] set_location_assignment PIN_60 -to R_in[6] set_location_assignment PIN_61 -to R_in[7] set_location_assignment PIN_88 -to B_in[7] set_location_assignment PIN_87 -to B_in[6] set_location_assignment PIN_86 -to B_in[5] set_location_assignment PIN_85 -to B_in[4] set_location_assignment PIN_83 -to B_in[3] set_location_assignment PIN_80 -to B_in[2] set_location_assignment PIN_77 -to B_in[1] set_location_assignment PIN_89 -to PCLK_in set_location_assignment PIN_76 -to B_in[0] set_location_assignment PIN_90 -to HSYNC_in set_location_assignment PIN_91 -to VSYNC_in set_location_assignment PIN_98 -to FID_in set_location_assignment PIN_72 -to G_in[7] set_location_assignment PIN_71 -to G_in[6] set_location_assignment PIN_69 -to G_in[5] set_location_assignment PIN_68 -to G_in[4] set_location_assignment PIN_67 -to G_in[3] set_location_assignment PIN_66 -to G_in[2] set_location_assignment PIN_65 -to G_in[1] set_location_assignment PIN_64 -to G_in[0] #============================================================ # HDMITX #============================================================ set_location_assignment PIN_113 -to HDMI_TX_PCLK set_location_assignment PIN_111 -to HDMI_TX_BD[3] set_location_assignment PIN_112 -to HDMI_TX_BD[4] set_location_assignment PIN_110 -to HDMI_TX_BD[2] set_location_assignment PIN_106 -to HDMI_TX_BD[1] set_location_assignment PIN_105 -to HDMI_TX_BD[0] set_location_assignment PIN_104 -to HDMI_TX_DE set_location_assignment PIN_103 -to HDMI_TX_HS set_location_assignment PIN_101 -to HDMI_TX_VS set_location_assignment PIN_114 -to HDMI_TX_BD[5] set_location_assignment PIN_115 -to HDMI_TX_BD[6] set_location_assignment PIN_119 -to HDMI_TX_BD[7] set_location_assignment PIN_120 -to HDMI_TX_GD[0] set_location_assignment PIN_121 -to HDMI_TX_GD[1] set_location_assignment PIN_125 -to HDMI_TX_GD[2] set_location_assignment PIN_132 -to HDMI_TX_GD[3] set_location_assignment PIN_133 -to HDMI_TX_GD[4] set_location_assignment PIN_134 -to HDMI_TX_GD[5] set_location_assignment PIN_135 -to HDMI_TX_GD[6] set_location_assignment PIN_136 -to HDMI_TX_GD[7] set_location_assignment PIN_137 -to HDMI_TX_RD[0] set_location_assignment PIN_141 -to HDMI_TX_RD[1] set_location_assignment PIN_142 -to HDMI_TX_RD[2] set_location_assignment PIN_143 -to HDMI_TX_RD[3] set_location_assignment PIN_144 -to HDMI_TX_RD[4] set_location_assignment PIN_7 -to HDMI_TX_RD[5] set_location_assignment PIN_10 -to HDMI_TX_RD[6] set_location_assignment PIN_11 -to HDMI_TX_RD[7] set_location_assignment PIN_100 -to HDMI_TX_INT_N set_location_assignment PIN_127 -to HDMI_TX_MODE #============================================================ # SD card #============================================================ set_location_assignment PIN_32 -to SD_CLK set_location_assignment PIN_31 -to SD_CMD set_location_assignment PIN_33 -to SD_DAT[0] set_location_assignment PIN_39 -to SD_DAT[1] set_location_assignment PIN_28 -to SD_DAT[2] set_location_assignment PIN_30 -to SD_DAT[3] #============================================================ # Leds #============================================================ set_location_assignment PIN_44 -to LED_G set_location_assignment PIN_46 -to LED_R #============================================================ # I2C #============================================================ set_location_assignment PIN_49 -to sda set_location_assignment PIN_50 -to scl #============================================================ # Char LCD #============================================================ set_location_assignment PIN_42 -to LCD_RS set_location_assignment PIN_43 -to LCD_CS_N set_location_assignment PIN_51 -to LCD_BL #============================================================ # Buttons #============================================================ set_location_assignment PIN_129 -to btn[1] set_location_assignment PIN_128 -to btn[0] set_instance_assignment -name PLL_COMPENSATE ON -to G_in set_instance_assignment -name PLL_COMPENSATE ON -to FID_in set_instance_assignment -name PLL_COMPENSATE ON -to HSYNC_in set_instance_assignment -name PLL_COMPENSATE ON -to R_in set_instance_assignment -name PLL_COMPENSATE ON -to VSYNC_in set_instance_assignment -name PLL_COMPENSATE ON -to B_in set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall set_global_assignment -name SEARCH_PATH rtl set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE" set_global_assignment -name ALLOW_REGISTER_RETIMING OFF set_global_assignment -name ENABLE_OCT_DONE OFF set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name GENERATE_RBF_FILE ON set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP" set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 50% #set_location_assignment PLL_4 -to "scanconverter:scanconverter_inst|pll_3x:pll_linetriple|altpll:altpll_component|pll_3x_altpll:auto_generated|pll1" #set_location_assignment PLL_3 -to "scanconverter:scanconverter_inst|pll_3x_lowfreq:pll_linetriple_lowfreq|altpll:altpll_component|pll_3x_lowfreq_altpll:auto_generated|pll1" #set_location_assignment PLL_1 -to "scanconverter:scanconverter_inst|pll_2x:pll_linedouble|altpll:altpll_component|pll_2x_altpll:auto_generated|pll1" set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 8.0 set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 2.0 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name VERILOG_FILE rtl/videogen.v set_global_assignment -name QIP_FILE software/sys_controller/mem_init/meminit.qip set_global_assignment -name VERILOG_FILE rtl/ir_rcv.v set_global_assignment -name SDC_FILE ossc.sdc set_global_assignment -name QSYS_FILE sys.qsys set_global_assignment -name VERILOG_FILE rtl/ossc.v set_global_assignment -name VERILOG_FILE rtl/scanconverter.v set_global_assignment -name QIP_FILE rtl/linebuf.qip set_global_assignment -name QIP_FILE rtl/pll_2x.qip set_global_assignment -name QIP_FILE rtl/pll_3x.qip set_global_assignment -name CDF_FILE output_files/Chain1.cdf set_global_assignment -name SIGNALTAP_FILE output_files/ossc_la.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top