mirror of
https://github.com/marqs85/ossc.git
synced 2024-11-16 00:05:01 +00:00
406 lines
14 KiB
Plaintext
406 lines
14 KiB
Plaintext
/*
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* linker.x - Linker script
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*
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* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
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* SOPC Builder design path: ../../sys.sopcinfo
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*
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* Generated: Sun Oct 16 12:18:06 EEST 2016
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*/
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/*
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* DO NOT MODIFY THIS FILE
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*
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* Changing this file will have subtle consequences
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* which will almost certainly lead to a nonfunctioning
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* system. If you do modify this file, be aware that your
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* changes will be overwritten and lost when this file
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* is generated again.
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*
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* DO NOT MODIFY THIS FILE
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*/
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/*
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* License Agreement
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*
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* Copyright (c) 2008
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* Altera Corporation, San Jose, California, USA.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This agreement shall be governed in all respects by the laws of the State
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* of California and by the laws of the United States of America.
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*/
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MEMORY
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{
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epcq_controller_0_avl_mem : ORIGIN = 0x0, LENGTH = 8388608
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reset : ORIGIN = 0x810000, LENGTH = 32
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onchip_memory2_0 : ORIGIN = 0x810020, LENGTH = 40928
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}
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/* Define symbols for each memory base-address */
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__alt_mem_epcq_controller_0_avl_mem = 0x0;
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__alt_mem_onchip_memory2_0 = 0x810000;
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OUTPUT_FORMAT( "elf32-littlenios2",
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"elf32-littlenios2",
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"elf32-littlenios2" )
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OUTPUT_ARCH( nios2 )
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ENTRY( _start )
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/*
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* The alt_load() facility is enabled. This typically happens when there isn't
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* an external bootloader (e.g. flash bootloader).
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* The LMA (aka physical address) of each loaded section is
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* set to the .text memory device.
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* The HAL alt_load() routine called from crt0 copies sections from
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* the .text memory to RAM as needed.
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*/
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SECTIONS
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{
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/*
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* Output sections associated with reset and exceptions (they have to be first)
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*/
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.entry :
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{
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KEEP (*(.entry))
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} > reset
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.exceptions :
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{
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PROVIDE (__ram_exceptions_start = ABSOLUTE(.));
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. = ALIGN(0x20);
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KEEP (*(.irq));
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KEEP (*(.exceptions.entry.label));
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KEEP (*(.exceptions.entry.user));
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KEEP (*(.exceptions.entry.ecc_fatal));
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KEEP (*(.exceptions.entry));
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KEEP (*(.exceptions.irqtest.user));
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KEEP (*(.exceptions.irqtest));
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KEEP (*(.exceptions.irqhandler.user));
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KEEP (*(.exceptions.irqhandler));
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KEEP (*(.exceptions.irqreturn.user));
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KEEP (*(.exceptions.irqreturn));
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KEEP (*(.exceptions.notirq.label));
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KEEP (*(.exceptions.notirq.user));
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KEEP (*(.exceptions.notirq));
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KEEP (*(.exceptions.soft.user));
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KEEP (*(.exceptions.soft));
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KEEP (*(.exceptions.unknown.user));
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KEEP (*(.exceptions.unknown));
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KEEP (*(.exceptions.exit.label));
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KEEP (*(.exceptions.exit.user));
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KEEP (*(.exceptions.exit));
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KEEP (*(.exceptions));
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PROVIDE (__ram_exceptions_end = ABSOLUTE(.));
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} > onchip_memory2_0
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PROVIDE (__flash_exceptions_start = LOADADDR(.exceptions));
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.text :
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{
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/*
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* All code sections are merged into the text output section, along with
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* the read only data sections.
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*
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*/
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PROVIDE (stext = ABSOLUTE(.));
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*(.interp)
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*(.hash)
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*(.dynsym)
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*(.dynstr)
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*(.gnu.version)
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*(.gnu.version_d)
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*(.gnu.version_r)
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*(.rel.init)
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*(.rela.init)
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*(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
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*(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
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*(.rel.fini)
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*(.rela.fini)
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*(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
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*(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
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*(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
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*(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
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*(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
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*(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
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*(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
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*(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
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*(.rel.ctors)
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*(.rela.ctors)
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*(.rel.dtors)
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*(.rela.dtors)
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*(.rel.got)
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*(.rela.got)
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*(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
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*(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
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*(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
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*(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
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*(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
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*(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
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*(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
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*(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
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*(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
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*(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
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*(.rel.plt)
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*(.rela.plt)
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*(.rel.dyn)
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KEEP (*(.init))
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*(.plt)
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*(.text .stub .text.* .gnu.linkonce.t.*)
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning.*)
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KEEP (*(.fini))
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PROVIDE (__etext = ABSOLUTE(.));
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PROVIDE (_etext = ABSOLUTE(.));
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PROVIDE (etext = ABSOLUTE(.));
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*(.eh_frame_hdr)
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/* Ensure the __preinit_array_start label is properly aligned. We
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could instead move the label definition inside the section, but
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the linker would then create the section even if it turns out to
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be empty, which isn't pretty. */
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. = ALIGN(4);
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PROVIDE (__preinit_array_start = ABSOLUTE(.));
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*(.preinit_array)
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PROVIDE (__preinit_array_end = ABSOLUTE(.));
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PROVIDE (__init_array_start = ABSOLUTE(.));
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*(.init_array)
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PROVIDE (__init_array_end = ABSOLUTE(.));
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PROVIDE (__fini_array_start = ABSOLUTE(.));
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*(.fini_array)
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PROVIDE (__fini_array_end = ABSOLUTE(.));
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SORT(CONSTRUCTORS)
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KEEP (*(.eh_frame))
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*(.gcc_except_table .gcc_except_table.*)
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*(.dynamic)
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PROVIDE (__CTOR_LIST__ = ABSOLUTE(.));
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KEEP (*(.ctors))
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KEEP (*(SORT(.ctors.*)))
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PROVIDE (__CTOR_END__ = ABSOLUTE(.));
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PROVIDE (__DTOR_LIST__ = ABSOLUTE(.));
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KEEP (*(.dtors))
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KEEP (*(SORT(.dtors.*)))
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PROVIDE (__DTOR_END__ = ABSOLUTE(.));
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KEEP (*(.jcr))
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. = ALIGN(4);
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} > onchip_memory2_0 = 0x3a880100 /* NOP instruction (always in big-endian byte ordering) */
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.rodata :
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{
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PROVIDE (__ram_rodata_start = ABSOLUTE(.));
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. = ALIGN(4);
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*(.rodata .rodata.* .gnu.linkonce.r.*)
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*(.rodata1)
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. = ALIGN(4);
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PROVIDE (__ram_rodata_end = ABSOLUTE(.));
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} > onchip_memory2_0
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PROVIDE (__flash_rodata_start = LOADADDR(.rodata));
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/*
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*
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* This section's LMA is set to the .text region.
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* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
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*
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* .rwdata region equals the .text region, and is set to be loaded into .text region.
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* This requires two copies of .rwdata in the .text region. One read writable at VMA.
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* and one read-only at LMA. crt0 will copy from LMA to VMA on reset
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*
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*/
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.rwdata LOADADDR (.rodata) + SIZEOF (.rodata) : AT ( LOADADDR (.rodata) + SIZEOF (.rodata)+ SIZEOF (.rwdata) )
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{
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PROVIDE (__ram_rwdata_start = ABSOLUTE(.));
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. = ALIGN(4);
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*(.got.plt) *(.got)
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*(.data1)
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*(.data .data.* .gnu.linkonce.d.*)
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_gp = ABSOLUTE(. + 0x8000);
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PROVIDE(gp = _gp);
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*(.rwdata .rwdata.*)
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*(.sdata .sdata.* .gnu.linkonce.s.*)
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*(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
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. = ALIGN(4);
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_edata = ABSOLUTE(.);
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PROVIDE (edata = ABSOLUTE(.));
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PROVIDE (__ram_rwdata_end = ABSOLUTE(.));
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} > onchip_memory2_0
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PROVIDE (__flash_rwdata_start = LOADADDR(.rwdata));
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/*
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*
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* This section's LMA is set to the .text region.
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* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
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*
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*/
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.bss LOADADDR (.rwdata) + SIZEOF (.rwdata) : AT ( LOADADDR (.rwdata) + SIZEOF (.rwdata) )
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{
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__bss_start = ABSOLUTE(.);
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PROVIDE (__sbss_start = ABSOLUTE(.));
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PROVIDE (___sbss_start = ABSOLUTE(.));
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*(.dynsbss)
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*(.sbss .sbss.* .gnu.linkonce.sb.*)
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*(.sbss2 .sbss2.* .gnu.linkonce.sb2.*)
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*(.scommon)
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PROVIDE (__sbss_end = ABSOLUTE(.));
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PROVIDE (___sbss_end = ABSOLUTE(.));
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*(.dynbss)
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*(.bss .bss.* .gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN(4);
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__bss_end = ABSOLUTE(.);
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} > onchip_memory2_0
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/*
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*
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* One output section mapped to the associated memory device for each of
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* the available memory devices. These are not used by default, but can
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* be used by user applications by using the .section directive.
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*
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* The output section used for the heap is treated in a special way,
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* i.e. the symbols "end" and "_end" are added to point to the heap start.
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*
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* Because alt_load() is enabled, these sections have
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* their LMA set to be loaded into the .text memory region.
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* However, the alt_load() code will NOT automatically copy
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* these sections into their mapped memory region.
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*
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*/
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/*
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*
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* This section's LMA is set to the .text region.
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* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
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*
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*/
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.epcq_controller_0_avl_mem : AT ( LOADADDR (.bss) + SIZEOF (.bss) )
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{
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PROVIDE (_alt_partition_epcq_controller_0_avl_mem_start = ABSOLUTE(.));
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*(.epcq_controller_0_avl_mem .epcq_controller_0_avl_mem. epcq_controller_0_avl_mem.*)
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. = ALIGN(4);
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PROVIDE (_alt_partition_epcq_controller_0_avl_mem_end = ABSOLUTE(.));
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} > epcq_controller_0_avl_mem
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PROVIDE (_alt_partition_epcq_controller_0_avl_mem_load_addr = LOADADDR(.epcq_controller_0_avl_mem));
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/*
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*
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* This section's LMA is set to the .text region.
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* crt0 will copy to this section's specified mapped region virtual memory address (VMA)
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*
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*/
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.onchip_memory2_0 LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) : AT ( LOADADDR (.epcq_controller_0_avl_mem) + SIZEOF (.epcq_controller_0_avl_mem) )
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{
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PROVIDE (_alt_partition_onchip_memory2_0_start = ABSOLUTE(.));
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*(.onchip_memory2_0 .onchip_memory2_0. onchip_memory2_0.*)
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. = ALIGN(4);
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PROVIDE (_alt_partition_onchip_memory2_0_end = ABSOLUTE(.));
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_end = ABSOLUTE(.);
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end = ABSOLUTE(.);
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__alt_stack_base = ABSOLUTE(.);
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} > onchip_memory2_0
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PROVIDE (_alt_partition_onchip_memory2_0_load_addr = LOADADDR(.onchip_memory2_0));
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/*
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* Stabs debugging sections.
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*
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*/
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.stab 0 : { *(.stab) }
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.stabstr 0 : { *(.stabstr) }
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.stab.excl 0 : { *(.stab.excl) }
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.stab.exclstr 0 : { *(.stab.exclstr) }
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.stab.index 0 : { *(.stab.index) }
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.stab.indexstr 0 : { *(.stab.indexstr) }
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.comment 0 : { *(.comment) }
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/* DWARF debug sections.
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Symbols in the DWARF debugging sections are relative to the beginning
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of the section so we begin them at 0. */
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/* DWARF 1 */
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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/* GNU DWARF 1 extensions */
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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/* DWARF 1.1 and DWARF 2 */
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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/* DWARF 2 */
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.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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/* SGI/MIPS DWARF 2 extensions */
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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/* Altera debug extensions */
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.debug_alt_sim_info 0 : { *(.debug_alt_sim_info) }
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}
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/* provide a pointer for the stack */
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/*
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* Don't override this, override the __alt_stack_* symbols instead.
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*/
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__alt_data_end = 0x81a000;
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/*
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* The next two symbols define the location of the default stack. You can
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* override them to move the stack to a different memory.
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*/
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PROVIDE( __alt_stack_pointer = __alt_data_end );
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PROVIDE( __alt_stack_limit = __alt_stack_base );
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/*
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* This symbol controls where the start of the heap is. If the stack is
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* contiguous with the heap then the stack will contract as memory is
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* allocated to the heap.
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|
* Override this symbol to put the heap in a different memory.
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*/
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PROVIDE( __alt_heap_start = end );
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|
PROVIDE( __alt_heap_limit = 0x81a000 );
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