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167 lines
7.5 KiB
C
167 lines
7.5 KiB
C
#ifndef __ALT_EXCEPTIONS_H__
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#define __ALT_EXCEPTIONS_H__
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/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* *
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******************************************************************************/
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#include "alt_types.h"
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#include "system.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif /* __cplusplus */
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/*
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* This file defines instruction-generated exception handling and registry
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* API, exception type enumeration, and handler return value enumeration for
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* Nios II.
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*/
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/*
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* The following enumeration describes the value in the CPU EXCEPTION
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* register CAUSE bit field.
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*/
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enum alt_exception_cause_e {
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/*
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* This value is passed to an exception handler's cause argument if
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* "extra exceptions" information (EXECPTION) register is not
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* present in the processor hardware configuration.
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*/
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NIOS2_EXCEPTION_CAUSE_NOT_PRESENT = -1,
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/*
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* Real values
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*/
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NIOS2_EXCEPTION_RESET = 0,
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NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1,
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NIOS2_EXCEPTION_INTERRUPT = 2,
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NIOS2_EXCEPTION_TRAP_INST = 3,
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NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4,
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NIOS2_EXCEPTION_ILLEGAL_INST = 5,
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NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6,
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NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7,
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NIOS2_EXCEPTION_DIVISION_ERROR = 8,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10,
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NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11,
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NIOS2_EXCEPTION_TLB_MISS = 12,
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NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13,
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NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14,
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NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15,
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NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16,
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NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17,
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NIOS2_EXCEPTION_ECC_TLB_ERR = 18,
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NIOS2_EXCEPTION_ECC_FETCH_ERR = 19,
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NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20,
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NIOS2_EXCEPTION_ECC_DATA_ERR = 21,
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NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
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};
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typedef enum alt_exception_cause_e alt_exception_cause;
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/*
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* These define valid return values for a user-defined instruction-generated
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* exception handler. The handler should return one of these to indicate
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* whether to re-issue the instruction that triggered the exception, or to
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* skip it.
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*/
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enum alt_exception_result_e {
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NIOS2_EXCEPTION_RETURN_REISSUE_INST = 0,
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NIOS2_EXCEPTION_RETURN_SKIP_INST = 1
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};
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typedef enum alt_exception_result_e alt_exception_result;
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/*
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* alt_instruction_exception_register() can be used to register an exception
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* handler for instruction-generated exceptions that are not handled by the
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* built-in exception handler (i.e. for interrupts).
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*
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* The registry API is optionally enabled through the "Enable
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* Instruction-related Exception API" HAL BSP setting, which will
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* define the macro below.
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*/
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#ifdef ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API
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void alt_instruction_exception_register (
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alt_exception_result (*exception_handler)(
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alt_exception_cause cause,
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alt_u32 exception_pc,
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alt_u32 bad_addr) );
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#endif /*ALT_INCLUDE_INSTRUCTION_RELATED_EXCEPTION_API */
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/*
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* alt_exception_cause_generated_bad_addr() indicates whether a particular
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* exception cause value was from an exception-type that generated a valid
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* address in the BADADDR register. The contents of BADADDR is passed to
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* a user-registered exception handler in all cases, whether valid or not.
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* This routine should be called to validate the bad_addr argument to
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* your exception handler.
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*
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* Note that this routine will return false (0) for causes
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* NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR.
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* You must read the TLBMISC.D field to determine if BADADDR
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* is valid for these (valid if TLBMISC.D = 1).
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*/
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int alt_exception_cause_generated_bad_addr(alt_exception_cause cause);
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/*
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* alt_ecc_fatal_exception_register() is called to register a handler to
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* service likely fatal ECC error exceptions. Likely the handler will
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* assume that correct execution of the running software is not possible
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* and re-initialize the processor (e.g. jump to reset address).
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*
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* Passing null (0x0) in the handler argument will disable a previously-
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* registered handler.
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*
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* Note that if no handler is registered, just normal exception processing
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* occurs on a likely fatal ECC exception and the exception processing
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* code might trigger an infinite exception loop.
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*
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* Note that the handler isn't a C function: it must be written in
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* assembly-code because it doesn't support C language calling conventions
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* and it can't return.
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*
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* The handler code must be carefully written to avoid triggering
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* another fatal ECC exception and creating an infinite exception loop.
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* The handler must avoid reading registers in case the fatal ECC
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* error is a register file ECC error.
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* If a data cache is present, the handler must avoid instructions that
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* access the data cache in case the fatal ECC error is a data cache
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* related ECC error. This includes cacheable load, cacheable store,
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* non-cacheable store (because it looks in the data cache to update the
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* data cache if it hits), and all data cache management instructions except
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* for INITD.
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*/
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void alt_ecc_fatal_exception_register(alt_u32 handler);
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __ALT_EXCEPTIONS_H__ */
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