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9d496383c3
* replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl
8 lines
514 B
Plaintext
8 lines
514 B
Plaintext
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
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set_global_assignment -name IP_TOOL_VERSION "17.1"
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set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_2x.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_inst.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x_bb.v"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_2x.ppf"]
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