marqs 9d496383c3 optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl		2019-10-06 23:54:32 +03:00
..
altera_avalon_jtag_uart_fd.h
altera_avalon_jtag_uart_regs.h
altera_avalon_jtag_uart.h
altera_avalon_pio_regs.h
altera_avalon_timer_regs.h	integrate zero-riscy	2018-10-06 13:19:12 +03:00
altera_avalon_timer.h	integrate zero-riscy	2018-10-06 13:19:12 +03:00
altera_epcq_controller_mod_regs.h	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00
altera_epcq_controller_mod.h	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00
i2c_opencores_regs.h	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00
i2c_opencores.h	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00
osd_generator_regs.h	first OSD implementation	2019-10-03 02:03:43 +03:00
pll_reconfig_regs.h	optimize clock network	2019-10-06 23:54:32 +03:00
sc_config_regs.h	use symlinks for SW IP BSP files	2019-09-30 18:56:27 +03:00