marqs 9d496383c3 optimize clock network ... * replace all clock muxes with a single cycloneive_clkctrl to minimize skew * use a single dynamically configured PLL to comply with cycloneive_clkctrl		2019-10-06 23:54:32 +03:00
..
drivers	optimize clock network	2019-10-06 23:54:32 +03:00
HAL
alt_sys_init.c
create-this-bsp
libhal_bsp.a	optimize clock network	2019-10-06 23:54:32 +03:00
linker.h
linker.x
Makefile
mem_init.mk
memory.gdb
public.mk
settings.bsp
system.h	optimize clock network	2019-10-06 23:54:32 +03:00