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d80a9fbb0c
Quartus calculates fmax (the theoretical maximum clock rate) based on the entirety of the logic between registers. In the case of the pclk_* lines, this includes some invalid paths which cross between the 3x <-> 2x and 5x <-> 4x clock domains. This is because these clocks share output pins from the PLL, but the PLL is configured to output only one of these clocks at a time, and the correct output from the logic is selected via a multiplexer. Therefore these paths cannot co-occur. This has the effect of increasing the calculated fmax of these paths to: pclk_3x: 107.98 MHz -> 132.52 MHz pclk_5x: 162.23 MHz -> 170.33 MHz
104 lines
6.8 KiB
Tcl
104 lines
6.8 KiB
Tcl
### CPU clock constraints ###
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create_clock -period 27MHz -name clk27 [get_ports clk27]
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set_input_delay -clock clk27 0 [get_ports {sda scl SD_CMD SD_DAT* *ALTERA_DATA0}]
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set_false_path -from [get_ports {btn* ir_rx HDMI_TX_INT_N HDMI_TX_MODE}]
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set_false_path -to {sys:sys_inst|sys_pio_1:pio_1|readdata*}
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### Scanconverter clock constraints ###
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create_clock -period 108MHz -name pclk_1x [get_ports PCLK_in]
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create_clock -period 33MHz -name pclk_2x_source [get_ports PCLK_in] -add
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create_clock -period 33MHz -name pclk_3x_source [get_ports PCLK_in] -add
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create_clock -period 33MHz -name pclk_4x_source [get_ports PCLK_in] -add
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create_clock -period 33MHz -name pclk_5x_source [get_ports PCLK_in] -add
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#derive_pll_clocks
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create_generated_clock -name pclk_2x -master_clock pclk_2x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 2 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
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create_generated_clock -name pclk_3x -master_clock pclk_3x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 3 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
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create_generated_clock -name pclk_4x -master_clock pclk_4x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 4 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
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create_generated_clock -name pclk_5x -master_clock pclk_5x_source -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[1]} -multiply_by 5 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[1]} -add
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create_generated_clock -name pclk_27mhz -master_clock clk27 -source {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 1 -duty_cycle 50.00 {scanconverter_inst|pll_pclk|altpll_component|auto_generated|pll1|clk[0]} -add
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# retrieve post-mapping clkmux output pin
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set clkmux_output [get_pins scanconverter_inst|clkctrl1|outclk]
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# specify postmux clocks which clock postprocess pipeline
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create_generated_clock -name pclk_1x_postmux -master_clock pclk_1x -source [get_pins scanconverter_inst|clkctrl1|inclk[0]] -multiply_by 1 $clkmux_output
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create_generated_clock -name pclk_2x_postmux -master_clock pclk_2x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
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create_generated_clock -name pclk_3x_postmux -master_clock pclk_3x -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
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create_generated_clock -name pclk_4x_postmux -master_clock pclk_4x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
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create_generated_clock -name pclk_5x_postmux -master_clock pclk_5x -source [get_pins scanconverter_inst|clkctrl1|inclk[3]] -multiply_by 1 $clkmux_output -add
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create_generated_clock -name pclk_27mhz_postmux -master_clock pclk_27mhz -source [get_pins scanconverter_inst|clkctrl1|inclk[2]] -multiply_by 1 $clkmux_output -add
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# specify output clocks that drive PCLK output pin
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set pclk_out_port [get_ports HDMI_TX_PCLK]
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create_generated_clock -name pclk_1x_out -master_clock pclk_1x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port
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create_generated_clock -name pclk_2x_out -master_clock pclk_2x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
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create_generated_clock -name pclk_3x_out -master_clock pclk_3x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
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create_generated_clock -name pclk_4x_out -master_clock pclk_4x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
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create_generated_clock -name pclk_5x_out -master_clock pclk_5x_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
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create_generated_clock -name pclk_27mhz_out -master_clock pclk_27mhz_postmux -source $clkmux_output -multiply_by 1 $pclk_out_port -add
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derive_clock_uncertainty
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# input delay constraints
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set TVP_dmin 0
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set TVP_dmax 1.5
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set critinputs [get_ports {R_in* G_in* B_in* HSYNC_in VSYNC_in FID_in}]
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foreach_in_collection c [get_clocks "pclk_1x pclk_*_source"] {
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set_input_delay -clock $c -min $TVP_dmin $critinputs -add_delay
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set_input_delay -clock $c -max $TVP_dmax $critinputs -add_delay
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}
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# output delay constraints
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set IT_Tsu 1.0
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set IT_Th -0.5
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set critoutputs_hdmi [get_ports {HDMI_TX_RD* HDMI_TX_GD* HDMI_TX_BD* HDMI_TX_DE HDMI_TX_HS HDMI_TX_VS}]
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foreach_in_collection c [get_clocks pclk_*_out] {
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set_output_delay -clock $c -min $IT_Th $critoutputs_hdmi -add
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set_output_delay -clock $c -max $IT_Tsu $critoutputs_hdmi -add
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}
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set_false_path -to [remove_from_collection [all_outputs] $critoutputs_hdmi]
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### CPU/scanconverter clock relations ###
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# Treat CPU clock asynchronous to pixel clocks
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set_clock_groups -asynchronous -group \
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{clk27 pclk_27mhz pclk_27mhz_postmux pclk_27mhz_out} \
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{pclk_1x pclk_1x_postmux pclk_1x_out} \
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{pclk_2x_source pclk_2x pclk_2x_postmux pclk_2x_out} \
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{pclk_3x_source pclk_3x pclk_3x_postmux pclk_3x_out} \
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{pclk_4x_source pclk_4x pclk_4x_postmux pclk_4x_out} \
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{pclk_5x_source pclk_5x pclk_5x_postmux pclk_5x_out}
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# Ignore paths from registers which are updated only at leading edge of vsync
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set_false_path -from [get_registers {scanconverter_inst|H_* scanconverter_inst|V_* scanconverter_inst|X_* scanconverter_inst|SL_* scanconverter_inst|LT_POS_*}]
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# Ignore paths from registers which are updated only at leading edge of hsync
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#set_false_path -from [get_registers {scanconverter:scanconverter_inst|line_idx scanconverter:scanconverter_inst|line_out_idx* scanconverter:scanconverter_inst|hmax*}]
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# Ignore paths that cross clock domains from 3x to 2x and 5x to 4x, since they share a clock line, but cannot co-occur.
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set_false_path -from [get_clocks {pclk_3x*}] -to [get_registers {scanconverter:scanconverter_inst|*_2x*}]
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set_false_path -from [get_clocks {pclk_5x*}] -to [get_registers {scanconverter:scanconverter_inst|*_4x*}]
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# Ignore paths to latency tester sync regs
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set_false_path -to [get_registers {lat_tester:lt0|mode_synced* lat_tester:lt0|VSYNC_in_* lat_tester:lt0|trigger_*}]
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### JTAG Signal Constraints ###
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#constrain the TCK port
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#create_clock -name tck -period "10MHz" [get_ports altera_reserved_tck]
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#cut all paths to and from tck
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set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]
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#constrain the TDI port
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set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]
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#constrain the TMS port
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set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]
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#constrain the TDO port
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#set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]
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