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109 lines
3.2 KiB
Verilog
109 lines
3.2 KiB
Verilog
//
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// Copyright (C) 2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`define LT_STATE_IDLE 2'h0
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`define LT_STATE_LAT_MEAS 2'h1
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`define LT_STATE_STB_MEAS 2'h2
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`define LT_STATE_FINISHED 2'h3
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module lat_tester (
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input clk27,
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input pclk,
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input active,
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input armed,
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input sensor,
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input trigger,
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input VSYNC_in,
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input [1:0] mode_in,
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output reg [2:0] mode_synced,
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output reg [15:0] lat_result,
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output reg [11:0] stb_result,
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output reg finished
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);
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reg VSYNC_in_L, VSYNC_in_LL, trigger_L, trigger_LL;
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reg [8:0] clk27_ctr;
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reg [1:0] state;
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always @(posedge pclk) begin
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VSYNC_in_L <= VSYNC_in;
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VSYNC_in_LL <= VSYNC_in_L;
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end
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always @(posedge pclk) begin
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if (VSYNC_in_LL && !VSYNC_in_L)
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mode_synced <= mode_in;
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end
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always @(posedge clk27) begin
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trigger_L <= trigger;
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trigger_LL <= trigger_L;
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end
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always @(posedge clk27) begin
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if (!active) begin
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state <= `LT_STATE_IDLE;
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end else begin
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case (state)
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default: begin //STATE_IDLE
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finished <= 1'b0;
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lat_result <= 0;
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stb_result <= 0;
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clk27_ctr <= 0;
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if (armed && trigger_LL)
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state <= `LT_STATE_LAT_MEAS;
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end
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`LT_STATE_LAT_MEAS: begin
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if (sensor==0) begin
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state <= `LT_STATE_STB_MEAS;
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clk27_ctr <= 0;
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end else if (lat_result==16'hffff) begin
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state <= `LT_STATE_FINISHED;
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end else begin
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if (clk27_ctr == 270-1) begin
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clk27_ctr <= 0;
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lat_result <= lat_result + 1'b1;
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end else begin
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clk27_ctr <= clk27_ctr + 1'b1;
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end
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end
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end
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`LT_STATE_STB_MEAS: begin
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if (((sensor==1) && (stb_result >= 12'd100)) || (stb_result == 12'hfff)) begin
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state <= `LT_STATE_FINISHED;
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end else begin
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if (clk27_ctr == 270-1) begin
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clk27_ctr <= 0;
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stb_result <= stb_result + 1'b1;
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end else begin
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clk27_ctr <= clk27_ctr + 1'b1;
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end
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end
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end
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`LT_STATE_FINISHED: begin
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finished <= 1'b1;
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if (!armed)
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state <= `LT_STATE_IDLE;
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end
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endcase
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end
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end
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endmodule
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