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mirror of https://github.com/marqs85/ossc.git synced 2024-06-26 17:29:57 +00:00
ossc/rtl
marqs db1cf5922f tvp7002 related robustness improvements
* bypass VSYNC processing
* enable raw SOG/HSYNC output
* add frontend RTL to read status from unprocessed signals
2023-01-31 20:49:08 +02:00
..
char_array.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
char_array.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
char_rom.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
char_rom.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
ir_rcv.v Improve IR receiver tolerance 2017-01-28 03:37:29 +02:00
lat_tester_includes.v Scanline updates and fixes 2019-03-23 00:09:46 +02:00
lat_tester.v use LEDs for debug in latency tester mode 2020-02-09 21:35:50 +02:00
linebuf.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
linebuf.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_hybr_ref_pre.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_hybr_ref_pre.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_hybr_ref.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_hybr_ref.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_sl.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
lpm_mult_4_sl.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
ossc.v advanced OSD implementation 2020-10-05 23:05:43 +03:00
pll_2x.ppf fix PLL reference clock switchover logic 2019-10-09 23:58:55 +03:00
pll_2x.qip update to Quartus 21.1 2022-12-27 14:59:47 +02:00
pll_2x.v update to Quartus 21.1 2022-12-27 14:59:47 +02:00
pll_config_2x_5x_data.mif optimize clock network 2019-10-06 23:54:32 +03:00
pll_config_3x_4x_data.mif optimize clock network 2019-10-06 23:54:32 +03:00
pll_config_default_data.mif fix PLL reference clock switchover logic 2019-10-09 23:58:55 +03:00
scanconverter.v optimize line3x timing 2020-06-14 20:07:24 +03:00
timescale.v Initial public release (FW 0.64) 2016-02-23 01:03:50 +02:00
tvp7002_frontend.v tvp7002 related robustness improvements 2023-01-31 20:49:08 +02:00
videogen.v fix linebuf read address timing bottleneck 2019-10-07 01:25:33 +03:00