mirror of
https://github.com/mnaberez/py65.git
synced 2024-07-03 05:29:27 +00:00
Added whitespace.
This commit is contained in:
Mike Naberezny
parent
421eac9233
commit
03805a5afd
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@ -210,7 +210,7 @@ class MPU:
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if self.flags & x:
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self.BranchRelAddr()
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else:
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self.pc+=1
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self.pc += 1
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def opCLR(self, x):
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self.flags &=~x
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@ -568,12 +568,12 @@ class MPU:
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@instruction(name="BIT", mode="abs", cycles=4)
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def inst_0x2c(self):
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self.opBIT(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="AND", mode="abs", cycles=4)
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def inst_0x2d(self):
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self.opAND(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="ROL", mode="abs", cycles=6)
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def inst_0x2e(self):
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@ -606,7 +606,7 @@ class MPU:
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@instruction(name="AND", mode="aby", cycles=4, extracycles=1)
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def inst_0x39(self):
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self.opAND(self.AbsoluteYAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="AND", mode="abx", cycles=4, extracycles=1)
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def inst_0x3d(self):
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@ -616,7 +616,7 @@ class MPU:
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@instruction(name="ROL", mode="abx", cycles=7)
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def inst_0x3e(self):
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self.opROL(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="RTI", mode="imp", cycles=6)
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def inst_0x40(self):
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@ -626,17 +626,17 @@ class MPU:
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@instruction(name="EOR", mode="inx", cycles=6)
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def inst_0x41(self):
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self.opEOR(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="EOR", mode="zpg", cycles=3)
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def inst_0x45(self):
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self.opEOR(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LSR", mode="zpg", cycles=5)
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def inst_0x46(self):
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self.opLSR(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="PHA", mode="imp", cycles=3)
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def inst_0x48(self):
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@ -667,7 +667,7 @@ class MPU:
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@instruction(name="EOR", mode="abs", cycles=4)
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def inst_0x4d(self):
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self.opEOR(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="LSR", mode="abs", cycles=6)
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def inst_0x4e(self):
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@ -681,17 +681,17 @@ class MPU:
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@instruction(name="EOR", mode="iny", cycles=5, extracycles=1)
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def inst_0x51(self):
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self.opEOR(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="EOR", mode="zpx", cycles=4)
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def inst_0x55(self):
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self.opEOR(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LSR", mode="zpx", cycles=6)
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def inst_0x56(self):
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self.opLSR(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CLI", mode="imp", cycles=2)
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def inst_0x58(self):
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@ -705,32 +705,32 @@ class MPU:
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@instruction(name="EOR", mode="abx", cycles=4, extracycles=1)
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def inst_0x5d(self):
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self.opEOR(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="LSR", mode="abx", cycles=7)
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def inst_0x5e(self):
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self.opLSR(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="RTS", mode="imp", cycles=6)
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def inst_0x60(self):
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self.pc=self.stPopWord()
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self.pc+=1
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self.pc += 1
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@instruction(name="ADC", mode="inx", cycles=6)
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def inst_0x61(self):
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self.opADC(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="ADC", mode="zpg", cycles=3)
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def inst_0x65(self):
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self.opADC(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="ROR", mode="zpg", cycles=5)
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def inst_0x66(self):
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self.opROR(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="PLA", mode="imp", cycles=4)
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def inst_0x68(self):
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@ -768,7 +768,7 @@ class MPU:
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@instruction(name="ROR", mode="abs", cycles=6)
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def inst_0x6e(self):
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self.opROR(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="BVS", mode="rel", cycles=2, extracycles=2)
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def inst_0x70(self):
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@ -777,17 +777,17 @@ class MPU:
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@instruction(name="ADC", mode="iny", cycles=5, extracycles=1)
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def inst_0x71(self):
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self.opADC(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="ADC", mode="zpx", cycles=4)
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def inst_0x75(self):
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self.opADC(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="ROR", mode="zpx", cycles=6)
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def inst_0x76(self):
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self.opROR(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="SEI", mode="imp", cycles=2)
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def inst_0x78(self):
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@ -796,37 +796,37 @@ class MPU:
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@instruction(name="ADC", mode="aby", cycles=4, extracycles=1)
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def inst_0x79(self):
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self.opADC(self.AbsoluteYAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="ADC", mode="abx", cycles=4, extracycles=1)
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def inst_0x7d(self):
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self.opADC(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="ROR", mode="abx", cycles=7)
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def inst_0x7e(self):
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self.opROR(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="STA", mode="inx", cycles=6)
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def inst_0x81(self):
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self.opSTA(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STY", mode="zpg", cycles=3)
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def inst_0x84(self):
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self.opSTY(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STA", mode="zpg", cycles=3)
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def inst_0x85(self):
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self.opSTA(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STX", mode="zpg", cycles=3)
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def inst_0x86(self):
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self.opSTX(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="DEY", mode="imp", cycles=2)
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def inst_0x88(self):
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@ -842,17 +842,17 @@ class MPU:
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@instruction(name="STY", mode="abs", cycles=4)
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def inst_0x8c(self):
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self.opSTY(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="STA", mode="abs", cycles=4)
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def inst_0x8d(self):
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self.opSTA(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="STX", mode="abs", cycles=4)
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def inst_0x8e(self):
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self.opSTX(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="BCC", mode="rel", cycles=2, extracycles=2)
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def inst_0x90(self):
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@ -861,22 +861,22 @@ class MPU:
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@instruction(name="STA", mode="iny", cycles=6)
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def inst_0x91(self):
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self.opSTA(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STY", mode="zpx", cycles=4)
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def inst_0x94(self):
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self.opSTY(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STA", mode="zpx", cycles=4)
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def inst_0x95(self):
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self.opSTA(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="STX", mode="zpy", cycles=4)
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def inst_0x96(self):
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self.opSTX(self.ZeroPageYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="TYA", mode="imp", cycles=2)
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def inst_0x98(self):
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@ -886,7 +886,7 @@ class MPU:
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@instruction(name="STA", mode="aby", cycles=5)
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def inst_0x99(self):
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self.opSTA(self.AbsoluteYAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="TXS", mode="imp", cycles=2)
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def inst_0x9a(self):
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@ -895,7 +895,7 @@ class MPU:
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@instruction(name="STA", mode="abx", cycles=5)
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def inst_0x9d(self):
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self.opSTA(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="LDY", mode="imm", cycles=2)
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def inst_0xa0(self):
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@ -905,7 +905,7 @@ class MPU:
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@instruction(name="LDA", mode="inx", cycles=6)
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def inst_0xa1(self):
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self.opLDA(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDX", mode="imm", cycles=2)
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def inst_0xa2(self):
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@ -915,17 +915,17 @@ class MPU:
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@instruction(name="LDY", mode="zpg", cycles=3)
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def inst_0xa4(self):
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self.opLDY(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDA", mode="zpg", cycles=3)
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def inst_0xa5(self):
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self.opLDA(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDX", mode="zpg", cycles=3)
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def inst_0xa6(self):
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self.opLDX(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="TAY", mode="imp", cycles=2)
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def inst_0xa8(self):
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@ -964,22 +964,22 @@ class MPU:
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@instruction(name="LDA", mode="iny", cycles=5, extracycles=1)
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def inst_0xb1(self):
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self.opLDA(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDY", mode="zpx", cycles=4)
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def inst_0xb4(self):
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self.opLDY(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDA", mode="zpx", cycles=4)
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def inst_0xb5(self):
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self.opLDA(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="LDX", mode="zpy", cycles=4)
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def inst_0xb6(self):
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self.opLDX(self.ZeroPageYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CLV", mode="imp", cycles=2)
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def inst_0xb8(self):
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@ -988,7 +988,7 @@ class MPU:
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@instruction(name="LDA", mode="aby", cycles=4, extracycles=1)
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def inst_0xb9(self):
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self.opLDA(self.AbsoluteYAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="TSX", mode="imp", cycles=2)
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def inst_0xba(self):
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@ -1018,7 +1018,7 @@ class MPU:
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@instruction(name="CMP", mode="inx", cycles=6)
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def inst_0xc1(self):
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self.opCMP(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CPY", mode="zpg", cycles=3)
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def inst_0xc4(self):
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@ -1074,17 +1074,17 @@ class MPU:
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@instruction(name="CMP", mode="iny", cycles=5, extracycles=1)
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def inst_0xd1(self):
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self.opCMP(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CMP", mode="zpx", cycles=4)
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def inst_0xd5(self):
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self.opCMP(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="DEC", mode="zpx", cycles=6)
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def inst_0xd6(self):
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self.opDECR(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CLD", mode="imp", cycles=2)
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def inst_0xd8(self):
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@ -1093,17 +1093,17 @@ class MPU:
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@instruction(name="CMP", mode="aby", cycles=4, extracycles=1)
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def inst_0xd9(self):
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self.opCMP(self.AbsoluteYAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="CMP", mode="abx", cycles=4, extracycles=1)
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def inst_0xdd(self):
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self.opCMP(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="DEC", mode="abx", cycles=7)
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def inst_0xde(self):
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self.opDECR(self.AbsoluteXAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="CPX", mode="imm", cycles=2)
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def inst_0xe0(self):
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@ -1113,22 +1113,22 @@ class MPU:
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@instruction(name="SBC", mode="inx", cycles=6)
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def inst_0xe1(self):
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self.opSBC(self.IndirectXAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="CPX", mode="zpg", cycles=3)
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def inst_0xe4(self):
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self.opCPX(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="SBC", mode="zpg", cycles=3)
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def inst_0xe5(self):
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self.opSBC(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="INC", mode="zpg", cycles=5)
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def inst_0xe6(self):
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self.opINCR(self.ZeroPageAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="INX", mode="imp", cycles=2)
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def inst_0xe8(self):
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@ -1148,17 +1148,17 @@ class MPU:
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@instruction(name="CPX", mode="abs", cycles=4)
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def inst_0xec(self):
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self.opCPX(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="SBC", mode="abs", cycles=4)
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def inst_0xed(self):
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self.opSBC(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="INC", mode="abs", cycles=6)
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def inst_0xee(self):
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self.opINCR(self.AbsoluteAddr)
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self.pc+=2
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self.pc += 2
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@instruction(name="BEQ", mode="rel", cycles=2, extracycles=2)
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def inst_0xf0(self):
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@ -1167,17 +1167,17 @@ class MPU:
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@instruction(name="SBC", mode="iny", cycles=5, extracycles=1)
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def inst_0xf1(self):
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self.opSBC(self.IndirectYAddr)
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self.pc+=1
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self.pc += 1
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@instruction(name="SBC", mode="zpx", cycles=4)
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def inst_0xf5(self):
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self.opSBC(self.ZeroPageXAddr)
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self.pc+=1
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self.pc += 1
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||||
@instruction(name="INC", mode="zpx", cycles=6)
|
||||
def inst_0xf6(self):
|
||||
self.opINCR(self.ZeroPageXAddr)
|
||||
self.pc+=1
|
||||
self.pc += 1
|
||||
|
||||
@instruction(name="SED", mode="imp", cycles=2)
|
||||
def inst_0xf8(self):
|
||||
|
|
@ -1186,15 +1186,15 @@ class MPU:
|
|||
@instruction(name="SBC", mode="aby", cycles=4, extracycles=1)
|
||||
def inst_0xf9(self):
|
||||
self.opSBC(self.AbsoluteYAddr)
|
||||
self.pc+=2
|
||||
self.pc += 2
|
||||
|
||||
@instruction(name="SBC", mode="abx", cycles=4, extracycles=1)
|
||||
def inst_0xfd(self):
|
||||
self.opSBC(self.AbsoluteXAddr)
|
||||
self.pc+=2
|
||||
self.pc += 2
|
||||
|
||||
@instruction(name="INC", mode="abx", cycles=7)
|
||||
def inst_0xfe(self):
|
||||
self.opINCR(self.AbsoluteXAddr)
|
||||
self.pc+=2
|
||||
self.pc += 2
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user