Rename mpu65Org16 to mpu65org16 for PEP8

2025-03-21 08:29:48 +00:00 · 2012-01-11 11:07:16 -08:00 · 2012-01-11 11:07:16 -08:00 · 819abb7a77
commit 819abb7a77
parent c98986c3f3
3 changed files with 2 additions and 2 deletions
--- a/README.markdown
+++ b/README.markdown
@ -36,7 +36,7 @@ The following devices are simulated at this time:
    than others. This simulation is based on the W65C02S from the Western
    Design Center (WDC).

- - `mpu65Org16` simulates the 65Org16, a 6502-like microprocessor with a 16-bit
+ - `mpu65org16` simulates the 65Org16, a 6502-like microprocessor with a 16-bit
   data bus and 32-bit address bus.  This microprocessor is a project of the
   [6502.org community](http://forum.6502.org/viewtopic.php?t=1824) and a
   [Verilog core](https://github.com/BigEd/verilog-6502/wiki) for it has been
--- a/src/py65/devices/mpu65Org16.py_
+++ b/src/py65/devices/mpu65Org16.py_
--- a/src/py65/monitor.py
+++ b/src/py65/monitor.py
@ -22,7 +22,7 @@ import urllib2
 from asyncore import compact_traceback
 from py65.devices.mpu6502 import MPU as NMOS6502
 from py65.devices.mpu65c02 import MPU as CMOS65C02
-from py65.devices.mpu65Org16 import MPU as V65Org16
+from py65.devices.mpu65org16 import MPU as V65Org16
 from py65.disassembler import Disassembler
 from py65.assembler import Assembler
 from py65.utils.addressing import AddressParser