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Note 65Org16 simulation module

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Mike Naberezny 2012-01-01 15:22:19 -08:00
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@ -1,5 +1,6 @@
0.11-dev *Next release* 0.11-dev *Next release*
- Added a new 65Org16 MPU simulation written by Ed Spittles.
0.10 (2011-08-27) 0.10 (2011-08-27)

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README.markdown
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@ -42,6 +42,12 @@ The following devices are simulated at this time:
than others. This simulation is based on the W65C02S from the Western than others. This simulation is based on the W65C02S from the Western
Design Center (WDC). Design Center (WDC).
- `mpu65Org16` simulates the 65Org16, a 6502-like microprocessor with a 16-bit
data bus and 32-bit address bus. This microprocessor is a project of the
[6502.org community](http://forum.6502.org/viewtopic.php?t=1824) and a
[Verilog core](https://github.com/BigEd/verilog-6502/wiki) for it has been
implemented.
## Monitor ## Monitor
Py65 includes a console-based machine language monitor (sometimes also called Py65 includes a console-based machine language monitor (sometimes also called
@ -71,5 +77,5 @@ These people are responsible for Py65:
- [Oscar Lindberg](http://github.com/offe) started the 65C02 simulation - [Oscar Lindberg](http://github.com/offe) started the 65C02 simulation
module and contributed greatly to its implementation. module and contributed greatly to its implementation.
- [Ed Spittles](http://github.com/biged) helped with testing and provided - [Ed Spittles](http://github.com/biged) wrote the 65Org16 simulation module
many useful issue reports and patches. and provided many useful issue reports and patches.