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https://github.com/mnaberez/py65.git
synced 2024-10-15 10:24:03 +00:00
Added 65C02 instructions SMB0 through SMB7.
This commit is contained in:
Mike Naberezny
parent
c902eed125
commit
ba3b42849a
@ -28,6 +28,10 @@ class MPU(NMOS6502):
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address = x()
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self.memory[address] &= mask
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def opSMB(self, x, mask):
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address = x()
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self.memory[address] |= mask
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def opSTZ(self, x):
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self.memory[x()] = 0x00
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@ -135,11 +139,21 @@ class MPU(NMOS6502):
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self.opRMB(self.ZeroPageAddr, 0x7F)
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self.pc += 1
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@instruction(name="SMB0", mode="zpg", cycles=5)
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def inst_0x87(self):
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self.opSMB(self.ZeroPageAddr, 0x01)
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self.pc += 1
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@instruction(name="STA", mode="zpi", cycles=5)
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def inst_0x92(self):
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self.opSTA(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="SMB1", mode="zpg", cycles=5)
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def inst_0x97(self):
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self.opSMB(self.ZeroPageAddr, 0x02)
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self.pc += 1
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@instruction(name="STZ", mode="abs", cycles=4)
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def inst_0x9c(self):
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self.opSTZ(self.AbsoluteAddr)
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@ -150,15 +164,45 @@ class MPU(NMOS6502):
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self.opSTZ(self.AbsoluteXAddr)
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self.pc += 2
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@instruction(name="SMB2", mode="zpg", cycles=5)
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def inst_0xa7(self):
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self.opSMB(self.ZeroPageAddr, 0x04)
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self.pc += 1
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@instruction(name="LDA", mode="zpi", cycles=5)
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def inst_0xb2(self):
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self.opLDA(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="SMB3", mode="zpg", cycles=5)
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def inst_0xb7(self):
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self.opSMB(self.ZeroPageAddr, 0x08)
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self.pc += 1
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@instruction(name="SMB4", mode="zpg", cycles=5)
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def inst_0xc7(self):
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self.opSMB(self.ZeroPageAddr, 0x10)
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self.pc += 1
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@instruction(name="SMB5", mode="zpg", cycles=5)
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def inst_0xd7(self):
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self.opSMB(self.ZeroPageAddr, 0x20)
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self.pc += 1
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@instruction(name="PHX", mode="imp", cycles=3)
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def inst_0xda(self):
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self.stPush(self.x)
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@instruction(name="SMB6", mode="zpg", cycles=5)
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def inst_0xe7(self):
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self.opSMB(self.ZeroPageAddr, 0x40)
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self.pc += 1
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@instruction(name="SMB7", mode="zpg", cycles=5)
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def inst_0xf7(self):
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self.opSMB(self.ZeroPageAddr, 0x80)
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self.pc += 1
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@instruction(name="PLX", mode="imp", cycles=4)
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def inst_0xfa(self):
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self.x = self.stPop()
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@ -469,6 +469,174 @@ class MPUTests(unittest.TestCase, Common6502Tests):
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self.assertEquals(0x00, mpu.a)
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self.assertEquals(flags, mpu.flags)
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# SMB0
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def test_smb0_sets_bit_0_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0x87, 0x43)) #=> SMB0 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00000001', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb0_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0x87, 0x43)) #=> SMB0 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB1
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def test_smb1_sets_bit_1_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0x97, 0x43)) #=> SMB1 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00000010', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb1_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0x97, 0x43)) #=> SMB1 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB2
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def test_smb2_sets_bit_2_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xA7, 0x43)) #=> SMB2 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00000100', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb2_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xA7, 0x43)) #=> SMB2 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB3
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def test_smb3_sets_bit_3_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xB7, 0x43)) #=> SMB3 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00001000', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb3_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xB7, 0x43)) #=> SMB3 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB4
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def test_smb4_sets_bit_4_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xC7, 0x43)) #=> SMB4 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00010000', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb4_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xC7, 0x43)) #=> SMB4 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB5
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def test_smb5_sets_bit_5_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xD7, 0x43)) #=> SMB5 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('00100000', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb5_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xD7, 0x43)) #=> SMB5 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB6
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def test_smb6_sets_bit_6_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xE7, 0x43)) #=> SMB6 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('01000000', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb6_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xE7, 0x43)) #=> SMB6 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SMB7
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def test_smb7_sets_bit_7_without_affecting_other_bits(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xF7, 0x43)) #=> SMB7 $43
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mpu.step()
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self.assertEquals(0x0002, mpu.pc)
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self.assertEquals(5, mpu.processorCycles)
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expected = int('10000000', 2)
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self.assertEquals(expected, mpu.memory[0x0043])
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def test_smb7_does_not_affect_status_register(self):
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mpu = self._make_mpu()
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mpu.memory[0x0043] = int('00000000',2)
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self._write(mpu.memory, 0x0000, (0xF7, 0x43)) #=> SMB7 $43
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expected = int('11001100', 2)
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mpu.flags = expected
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mpu.step()
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self.assertEquals(expected, mpu.flags)
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# SBC Zero Page, Indirect
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def test_sbc_zp_indirect_all_zeros_and_no_borrow_is_zero(self):
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