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Fix extracycles bug reported by David Turnbull.
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parent
276d5fc4f0
commit
c307b4858d
6
mpu.py
6
mpu.py
@ -87,7 +87,7 @@ class MPU:
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a1 = self.WordAt(self.ByteAt(self.pc))
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a1 = self.WordAt(self.ByteAt(self.pc))
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a2 = (a1+self.y)&0xffff
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a2 = (a1+self.y)&0xffff
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if ((a1&0xff00) != (a2&0xff00)):
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if ((a1&0xff00) != (a2&0xff00)):
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self.extracyles += 1
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self.extracycles += 1
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return a2
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return a2
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else:
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else:
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return (self.WordAt(self.ByteAt(self.pc))+self.y)&0xffff
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return (self.WordAt(self.ByteAt(self.pc))+self.y)&0xffff
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@ -100,7 +100,7 @@ class MPU:
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a1 = self.WordAt(self.pc)
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a1 = self.WordAt(self.pc)
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a2 = (a1+self.x)&0xffff
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a2 = (a1+self.x)&0xffff
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if ((a1&0xff00)!=(a2&0xff00)):
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if ((a1&0xff00)!=(a2&0xff00)):
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self.extracyles += 1;
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self.extracycles += 1
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return a2
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return a2
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else:
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else:
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return (self.WordAt(self.pc)+self.x)&0xffff
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return (self.WordAt(self.pc)+self.x)&0xffff
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@ -110,7 +110,7 @@ class MPU:
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a1 = self.WordAt(self.pc)
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a1 = self.WordAt(self.pc)
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a2=(a1+self.y)&0xffff
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a2=(a1+self.y)&0xffff
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if ((a1&0xff00)!=(a2&0xff00)):
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if ((a1&0xff00)!=(a2&0xff00)):
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self.extracyles += 1;
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self.extracycles += 1
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return a2
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return a2
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else:
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else:
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return (self.WordAt(self.pc)+self.y)&0xffff
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return (self.WordAt(self.pc)+self.y)&0xffff
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