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Fixed 6850 behaviour

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+ Fixed interrupt bit reset behaviour
This commit is contained in:
Izuan Nazrin 2017-05-30 01:33:12 +08:00
parent 356822df71
commit 92f8fe3dd9
1 changed files with 6 additions and 4 deletions
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10
src/main/java/com/loomcom/symon/devices/Acia6850.java
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@ -56,6 +56,9 @@ public class Acia6850 extends Acia {
public int read(int address, boolean cpuAccess) throws MemoryAccessException {
switch (address) {
case RX_REG:
if (cpuAccess) {
interrupt = false;
}
return rxRead(cpuAccess);
case STAT_REG:
return statusReg(cpuAccess);
@ -69,6 +72,9 @@ public class Acia6850 extends Acia {
public void write(int address, int data) throws MemoryAccessException {
switch (address) {
case TX_REG:
if (cpuAccess) {
interrupt = false;
}
txWrite(data);
break;
case CTRL_REG:
@ -113,10 +119,6 @@ public class Acia6850 extends Acia {
stat |= 0x80;
}
if (cpuAccess) {
interrupt = false;
}
return stat;
}