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Fixed 6850 behaviour
+ Fixed interrupt bit reset behaviour
This commit is contained in:
parent
356822df71
commit
92f8fe3dd9
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@ -56,6 +56,9 @@ public class Acia6850 extends Acia {
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public int read(int address, boolean cpuAccess) throws MemoryAccessException {
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public int read(int address, boolean cpuAccess) throws MemoryAccessException {
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switch (address) {
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switch (address) {
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case RX_REG:
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case RX_REG:
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if (cpuAccess) {
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interrupt = false;
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}
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return rxRead(cpuAccess);
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return rxRead(cpuAccess);
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case STAT_REG:
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case STAT_REG:
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return statusReg(cpuAccess);
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return statusReg(cpuAccess);
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@ -69,6 +72,9 @@ public class Acia6850 extends Acia {
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public void write(int address, int data) throws MemoryAccessException {
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public void write(int address, int data) throws MemoryAccessException {
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switch (address) {
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switch (address) {
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case TX_REG:
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case TX_REG:
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if (cpuAccess) {
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interrupt = false;
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}
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txWrite(data);
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txWrite(data);
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break;
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break;
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case CTRL_REG:
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case CTRL_REG:
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@ -113,10 +119,6 @@ public class Acia6850 extends Acia {
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stat |= 0x80;
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stat |= 0x80;
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}
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}
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if (cpuAccess) {
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interrupt = false;
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}
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return stat;
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return stat;
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}
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}
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