- Added more CRTC information to the README file.
- Added unit tests for the CRTC.
- Implemented register read for cursor position in the CRTC.
- Bundling a new version of jterminal that has correct backspace
behavior.
Introduces several changes requested by Mario Keller. The simulator now has a variable step count that can be selected by a drop-down box on the main window. This change also displays ASCII characters in the Memory window.
- Added tooltip text to status panel.
- Memory is no longer cleared on reset.
- Console can now receive key-strokes even while the simulator is
stopped (for single-stepping programs that require interaction)
- Updated screenshots with bug-fixed version.
The simulator now passes Klaus Dormann's 6502 Functional Test suite for
the first time.
Bug Fixes:
- PHP was not correctly setting the Break bit on the stack copy of the
processor status, so subsequent PLA's would not set the Break status
flag.
- The CPU had swapped NMI and IRQ reset vectors, so RTI was failing.
- BRK was pushing PC + 2 onto the stack, instead of PC + 1
- (Zero Page,X) addressing mode did not correctly wrap on zero page
boundaries.
- The instruction table used for disassembly had addressing modes
of LDA $B9 and $BD reversed. This did not affect behavior, only
disassembly of these instructions.
Other:
- Updated copyright date for 2013.
- Started migrating old JUnit 3 style tests to JUnit 4 annotations.
Adds a new view that displays a single page of memory (user selectable)
and allows direct editing of memory contents.
Also fixes several minor bugs, including one that prevented the status
pane from updating after each manual step.
- The UI layout has changed, and will likely change again in the future.
- Symon can now re-load ROM images from the File menu, under "Load ROM..."
- Font size can be changed under the "View" menu
This is something of a "Work in Progress" checkpoint of several features
that are all half baked:
1. Allow loading of 16KB ROM files at address $C000 at run-time, not
just at startup. See the "Load ROM..." File menu item.
2. Introduces the notion of "CPU Behaviors", so the core 6502 CPU
implementation can match the behavior of either an early NMOS 6502, late
NMOS 6502, or CMOS 65C02. Very little of this is actually implemented so
far.
3. Adds a completely bogus implementation of the 6522 VIA (it
does absolutely nothing right now).
4. Changes the address of the ACIA in the simulated system to match a
real hardware implementation I put together.
Bug Fixes:
- Fixed several bugs in the CPU that caused processor status flags to
be set incorrectly. Instructions affected were: STA, STX, STY, CMP,
CPX, CPY, BIT.
- Made some internal-use-only methods on the CPU class private.
- Fixed incorrect disassembly of (Indirect,X) and (Indirect),Y
instructions. Although this didn't affect behavior, it certainly
caused me some confusion in debugging.
- Added missing "BCS" instruction to instruction table.
Enhancements:
- Now includes a full version of Lee Davison's Enhanced 6502 BASIC
bundled as source code and a ROM image. Get that REAL COMPUTER
EXPERIENCE!(tm)
- If a file named "rom.bin" exists in the same directory where the
simulator is executed, it will be loaded at addresses $d000-$ffff.
- Gave the CPU an idle loop to make simulated timing a little more
realistic (but this is still an area needing major improvement)
- Changed the CPU's toString() method to give better debugging output.
- Added a small typeahead buffer to the Console.
- Better exception messaging.
Misc:
- Bumped version to 0.5, updated README.
