mirror of
https://github.com/sethm/symon.git
synced 2024-06-03 07:29:30 +00:00
b5a470d3ba
When describing the CPU's reset pin, the W65C02S data sheet says: > All Registers are initialized by software except the Decimal and Interrupt > disable mode select bits of the Processor Status Register (P) are initialized > by hardware. It then has a diagram of the power-on state of the processor status register: > 7 6 5 4 3 2 1 0 > * * 1 1 0 1 * * > N V - B D I Z C > > * = software initialized Confusingly the text indicates that only the D and I flags are initialised by hardware, while the diagram indicates that the B flag is initialised too. Meanwhile, https://www.nesdev.org/wiki/CPU_power_up_state says that the power-on state of the NES CPU is $34 (exactly matching the diagram above) but https://www.nesdev.org/wiki/Status_flags#The_B_flag says that the B flag does not physically exist within P register, it's only relevant in the copy of P that gets pushed to the stack by BRK (set), PHP (set), or an interrupt signal (cleared). As a result, the most sensible power-on state for the processor status register is with the "interrupt disable" flag set and everything else cleared.
104 lines
2.9 KiB
Java
104 lines
2.9 KiB
Java
package com.loomcom.symon;
|
|
|
|
import com.loomcom.symon.devices.Memory;
|
|
import com.loomcom.symon.exceptions.MemoryAccessException;
|
|
|
|
import junit.framework.TestCase;
|
|
|
|
public class CpuZeroPageYModeTest extends TestCase {
|
|
|
|
protected Cpu cpu;
|
|
protected Bus bus;
|
|
protected Memory mem;
|
|
|
|
protected void setUp() throws Exception {
|
|
this.cpu = new Cpu();
|
|
this.bus = new Bus(0x0000, 0xffff);
|
|
this.mem = new Memory(0x0000, 0xffff);
|
|
bus.addCpu(cpu);
|
|
bus.addDevice(mem);
|
|
|
|
// Load the reset vector.
|
|
bus.write(0xfffc, Bus.DEFAULT_LOAD_ADDRESS & 0x00ff);
|
|
bus.write(0xfffd, (Bus.DEFAULT_LOAD_ADDRESS & 0xff00) >>> 8);
|
|
|
|
cpu.reset();
|
|
// Assert initial state
|
|
assertEquals(0, cpu.getAccumulator());
|
|
assertEquals(0, cpu.getXRegister());
|
|
assertEquals(0, cpu.getYRegister());
|
|
assertEquals(0x200, cpu.getProgramCounter());
|
|
assertEquals(0xff, cpu.getStackPointer());
|
|
assertEquals(0x24, cpu.getProcessorStatus());
|
|
}
|
|
|
|
/*
|
|
* The following opcodes are tested for correctness in this file:
|
|
*
|
|
* STX - $96
|
|
* LDX - $b6
|
|
*
|
|
*/
|
|
|
|
/* STX - Store X Register - $96 */
|
|
|
|
public void test_STX() throws MemoryAccessException {
|
|
cpu.setYRegister(0x30);
|
|
cpu.setXRegister(0x00);
|
|
bus.loadProgram(0x96, 0x10); // STX $10,Y
|
|
cpu.step();
|
|
assertEquals(0x00, bus.read(0x40, true));
|
|
// Should have no effect on flags.
|
|
assertFalse(cpu.getZeroFlag());
|
|
assertFalse(cpu.getNegativeFlag());
|
|
|
|
cpu.reset();
|
|
cpu.setYRegister(0x30);
|
|
cpu.setXRegister(0x0f);
|
|
bus.loadProgram(0x96, 0x10); // STX $10,Y
|
|
cpu.step();
|
|
assertEquals(0x0f, bus.read(0x40, true));
|
|
assertFalse(cpu.getZeroFlag());
|
|
assertFalse(cpu.getNegativeFlag());
|
|
|
|
cpu.reset();
|
|
cpu.setYRegister(0x30);
|
|
cpu.setXRegister(0x80);
|
|
bus.loadProgram(0x96, 0x10); // STX $10,Y
|
|
cpu.step();
|
|
assertEquals(0x80, bus.read(0x40, true));
|
|
assertFalse(cpu.getZeroFlag());
|
|
assertFalse(cpu.getNegativeFlag());
|
|
}
|
|
|
|
/* LDX - Load X Register - $b6 */
|
|
|
|
public void test_LDX() throws MemoryAccessException {
|
|
bus.write(0x40, 0x00);
|
|
bus.write(0x41, 0x0f);
|
|
bus.write(0x42, 0x80);
|
|
|
|
bus.loadProgram(0xb6, 0x10,
|
|
0xb6, 0x11,
|
|
0xb6, 0x12);
|
|
|
|
cpu.setYRegister(0x30);
|
|
|
|
cpu.step();
|
|
assertEquals(0x00, cpu.getXRegister());
|
|
assertTrue(cpu.getZeroFlag());
|
|
assertFalse(cpu.getNegativeFlag());
|
|
|
|
cpu.step();
|
|
assertEquals(0x0f, cpu.getXRegister());
|
|
assertFalse(cpu.getZeroFlag());
|
|
assertFalse(cpu.getNegativeFlag());
|
|
|
|
cpu.step();
|
|
assertEquals(0x80, cpu.getXRegister());
|
|
assertFalse(cpu.getZeroFlag());
|
|
assertTrue(cpu.getNegativeFlag());
|
|
}
|
|
|
|
}
|