mirror of https://github.com/sethm/symon.git
310 lines
12 KiB
Java
310 lines
12 KiB
Java
/*
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* Copyright (c) 2008-2012 Seth J. Morabito <web@loomcom.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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package com.loomcom.symon;
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public interface InstructionTable {
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/**
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* Enumeration of valid CPU behaviors. These determine what behavior and instruction
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* set will be simulated, depending on desired version of 6502.
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*
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* TODO: As of version 0.6, this is still not used! All CPUs are "idealized" NMOS 6502 only.
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*/
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public enum CpuBehavior {
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/**
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* The earliest NMOS 6502 includes a bug that causes the ROR instruction
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* to behave like an ASL that does not affect the carry bit. This version
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* is very rare in the wild.
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*
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* NB: Does NOT implement "unimplemented" NMOS instructions.
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*/
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NMOS_WITH_ROR_BUG,
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/**
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* All NMOS 6502's have a bug with the indirect JMP instruction. If the
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*
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* NB: Does NOT implement "unimplemented" NMOS instructions.
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*/
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NMOS_WITH_INDIRECT_JMP_BUG,
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/**
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* Emulate an NMOS 6502 without the indirect JMP bug. This type of 6502
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* does not actually exist in the wild.
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*
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* NB: Does NOT implement "unimplemented" NMOS instructions.
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*/
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NMOS_WITHOUT_INDIRECT_JMP_BUG,
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/**
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* Emulate a CMOS 65C02, with all CMOS instructions and addressing modes.
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*/
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CMOS
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}
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/**
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* Enumeration of Addressing Modes.
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*/
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public enum Mode {
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ACC {
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public String toString() {
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return "Accumulator";
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}
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},
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ABS {
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public String toString() {
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return "Absolute";
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}
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},
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ABX {
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public String toString() {
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return "Absolute, X-indexed";
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}
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},
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ABY {
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public String toString() {
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return "Absolute, Y-indexed";
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}
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},
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IMM {
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public String toString() {
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return "Immediate";
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}
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},
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IMP {
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public String toString() {
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return "Implied";
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}
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},
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IND {
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public String toString() {
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return "Indirect";
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}
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},
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XIN {
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public String toString() {
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return "X-indexed Indirect";
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}
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},
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INY {
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public String toString() {
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return "Indirect, Y-indexed";
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}
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},
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REL {
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public String toString() {
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return "Relative";
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}
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},
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ZPG {
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public String toString() {
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return "Zeropage";
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}
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},
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ZPX {
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public String toString() {
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return "Zeropage, X-indexed";
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}
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},
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ZPY {
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public String toString() {
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return "Zeropage, Y-indexed";
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}
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},
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NUL {
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public String toString() {
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return "NULL";
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}
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}
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}
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// 6502 opcodes. No 65C02 opcodes implemented.
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/**
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* Instruction opcode names.
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*/
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public static final String[] opcodeNames = {
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"BRK", "ORA", null, null, null, "ORA", "ASL", null,
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"PHP", "ORA", "ASL", null, null, "ORA", "ASL", null,
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"BPL", "ORA", null, null, null, "ORA", "ASL", null,
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"CLC", "ORA", null, null, null, "ORA", "ASL", null,
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"JSR", "AND", null, null, "BIT", "AND", "ROL", null,
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"PLP", "AND", "ROL", null, "BIT", "AND", "ROL", null,
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"BMI", "AND", null, null, null, "AND", "ROL", null,
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"SEC", "AND", null, null, null, "AND", "ROL", null,
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"RTI", "EOR", null, null, null, "EOR", "LSR", null,
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"PHA", "EOR", "LSR", null, "JMP", "EOR", "LSR", null,
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"BVC", "EOR", null, null, null, "EOR", "LSR", null,
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"CLI", "EOR", null, null, null, "EOR", "LSR", null,
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"RTS", "ADC", null, null, null, "ADC", "ROR", null,
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"PLA", "ADC", "ROR", null, "JMP", "ADC", "ROR", null,
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"BVS", "ADC", null, null, null, "ADC", "ROR", null,
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"SEI", "ADC", null, null, null, "ADC", "ROR", null,
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"BCS", "STA", null, null, "STY", "STA", "STX", null,
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"DEY", null, "TXA", null, "STY", "STA", "STX", null,
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"BCC", "STA", null, null, "STY", "STA", "STX", null,
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"TYA", "STA", "TXS", null, null, "STA", null, null,
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"LDY", "LDA", "LDX", null, "LDY", "LDA", "LDX", null,
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"TAY", "LDA", "TAX", null, "LDY", "LDA", "LDX", null,
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"BCS", "LDA", null, null, "LDY", "LDA", "LDX", null,
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"CLV", "LDA", "TSX", null, "LDY", "LDA", "LDX", null,
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"CPY", "CMP", null, null, "CPY", "CMP", "DEC", null,
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"INY", "CMP", "DEX", null, "CPY", "CMP", "DEC", null,
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"BNE", "CMP", null, null, null, "CMP", "DEC", null,
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"CLD", "CMP", null, null, null, "CMP", "DEC", null,
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"CPX", "SBC", null, null, "CPX", "SBC", "INC", null,
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"INX", "SBC", "NOP", null, "CPX", "SBC", "INC", null,
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"BEQ", "SBC", null, null, null, "SBC", "INC", null,
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"SED", "SBC", null, null, null, "SBC", "INC", null
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};
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/**
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* Instruction addressing modes.
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*/
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public static final Mode[] instructionModes = {
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Mode.IMP, Mode.XIN, Mode.NUL, Mode.NUL, // 0x00-0x03
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Mode.NUL, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0x04-0x07
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Mode.IMP, Mode.IMM, Mode.ACC, Mode.NUL, // 0x08-0x0b
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Mode.NUL, Mode.ABS, Mode.ABS, Mode.NUL, // 0x0c-0x0f
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0x10-0x13
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0x14-0x17
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0x18-0x1b
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL, // 0x1c-0x1f
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Mode.ABS, Mode.XIN, Mode.NUL, Mode.NUL, // 0x20-0x23
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Mode.ZPG, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0x24-0x27
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Mode.IMP, Mode.IMM, Mode.ACC, Mode.NUL, // 0x28-0x2b
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0x2c-0x2f
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0x30-0x33
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0x34-0x37
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0x38-0x3b
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL, // 0x3c-0x3f
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Mode.IMP, Mode.XIN, Mode.NUL, Mode.NUL, // 0x40-0x43
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Mode.NUL, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0x44-0x47
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Mode.IMP, Mode.IMM, Mode.ACC, Mode.NUL, // 0x48-0x4b
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0x4c-0x4f
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0x50-0x53
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0x54-0x57
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0x58-0x5b
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL, // 0x5c-0x5f
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Mode.IMP, Mode.XIN, Mode.NUL, Mode.NUL, // 0x60-0x63
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Mode.NUL, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0x64-0x67
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Mode.IMP, Mode.IMM, Mode.ACC, Mode.NUL, // 0x68-0x6b
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Mode.IND, Mode.ABS, Mode.ABS, Mode.NUL, // 0x6c-0x6f
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0x70-0x73
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0x74-0x77
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0x78-0x7b
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL, // 0x7c-0x7f
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Mode.REL, Mode.XIN, Mode.NUL, Mode.NUL, // 0x80-0x83
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Mode.ZPG, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0x84-0x87
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Mode.IMP, Mode.NUL, Mode.IMP, Mode.NUL, // 0x88-0x8b
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0x8c-0x8f
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0x90-0x93
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Mode.ZPX, Mode.ZPX, Mode.ZPY, Mode.NUL, // 0x94-0x97
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Mode.IMP, Mode.ABY, Mode.IMP, Mode.NUL, // 0x98-0x9b
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Mode.NUL, Mode.ABX, Mode.NUL, Mode.NUL, // 0x9c-0x9f
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Mode.IMM, Mode.XIN, Mode.IMM, Mode.NUL, // 0xa0-0xa3
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Mode.ZPG, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0xa4-0xa7
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Mode.IMP, Mode.IMM, Mode.IMP, Mode.NUL, // 0xa8-0xab
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0xac-0xaf
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0xb0-0xb3
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Mode.ZPX, Mode.ZPX, Mode.ZPY, Mode.NUL, // 0xb4-0xb7
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Mode.IMP, Mode.ABY, Mode.IMP, Mode.NUL, // 0xb8-0xbb
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Mode.ABX, Mode.ABX, Mode.ABY, Mode.NUL, // 0xbc-0xbf
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Mode.IMM, Mode.XIN, Mode.NUL, Mode.NUL, // 0xc0-0xc3
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Mode.ZPG, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0xc4-0xc7
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Mode.IMP, Mode.IMM, Mode.IMP, Mode.NUL, // 0xc8-0xcb
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0xcc-0xcf
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0xd0-0xd3
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0xd4-0xd7
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0xd8-0xdb
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL, // 0xdc-0xdf
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Mode.IMM, Mode.XIN, Mode.NUL, Mode.NUL, // 0xe0-0xe3
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Mode.ZPG, Mode.ZPG, Mode.ZPG, Mode.NUL, // 0xe4-0xe7
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Mode.IMP, Mode.IMM, Mode.IMP, Mode.NUL, // 0xe8-0xeb
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Mode.ABS, Mode.ABS, Mode.ABS, Mode.NUL, // 0xec-0xef
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Mode.REL, Mode.INY, Mode.NUL, Mode.NUL, // 0xf0-0xf3
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Mode.NUL, Mode.ZPX, Mode.ZPX, Mode.NUL, // 0xf4-0xf7
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Mode.IMP, Mode.ABY, Mode.NUL, Mode.NUL, // 0xf8-0xfb
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Mode.NUL, Mode.ABX, Mode.ABX, Mode.NUL // 0xfc-0xff
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};
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/**
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* Size, in bytes, required for each instruction.
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*/
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public static final int[] instructionSizes = {
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1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 0, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,
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3, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,
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1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,
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1, 2, 0, 0, 0, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,
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2, 2, 0, 0, 2, 2, 2, 0, 1, 0, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 0, 3, 0, 0,
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2, 2, 2, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 2, 2, 2, 0, 1, 3, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0,
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2, 2, 0, 0, 2, 2, 2, 0, 1, 2, 1, 0, 3, 3, 3, 0,
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2, 2, 0, 0, 0, 2, 2, 0, 1, 3, 0, 0, 0, 3, 3, 0
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};
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/**
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* Number of clock cycles required for each instruction
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*/
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public static final int[] instructionClocks = {
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7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,
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6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,
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6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,
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6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,
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2, 6, 0, 0, 3, 3, 3, 0, 2, 0, 2, 0, 4, 4, 4, 0,
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2, 6, 0, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0,
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2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0,
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2, 5, 0, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0,
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2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0,
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2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0,
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2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0
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};
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}
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