(WIP) compiles now

Cpu6502.cpp

@@ -8,12 +8,13 @@
 #include "Cpu6502.h"
 #include "TransNetwork.h"
 #include "trans.h"
-#include "AddressBus.h"
+#include "addressbus.h"
 #include "Trace.h"
+#include "cpu.h"
 #include <iostream>
 
 
-
+#include "StateCalculator.h"
 
 
 
@@ -51,7 +52,7 @@ void Cpu6502::powerOn() {
      * temporary variable (see "step" method), we
      * need to initialize it here, to "phase one".
      */
-    segs[n->CLK0].on = true;
+    n->CLK0->on = true;
 
 
 
@@ -59,11 +60,23 @@ void Cpu6502::powerOn() {
     initPins();
 
     std::cout << "initial full calculation..." << std::endl;
-    recalcAll();
+    recalc(segs.all());
     dumpRegs();
     dumpSegs();
 }
 
+void Cpu6502::setSeg(Segment* s, bool on) {
+    s->set(on);
+}
+
+void Cpu6502::recalc(Segment* s) {
+    StateCalculator::recalc(s,n->VSS,n->VCC);
+}
+
+void Cpu6502::recalc(std::set<Segment*> s) {
+    StateCalculator::recalc(s,n->VSS,n->VCC);
+}
+
 void Cpu6502::initPins() {
     // set voltage supply and ground.
     setSeg(n->VCC, true);
@@ -115,7 +128,7 @@ void Cpu6502::step() {
      * 
      * The real 6502, of course, does not do this.
      */
-    const bool nextPhase = !segs[n->CLK0].on;
+    const bool nextPhase = !n->CLK0->on;
 
     clock(nextPhase);
     rw();
@@ -131,11 +144,11 @@ void Cpu6502::clock(bool phase) {
 
 void Cpu6502::rw() {
     // database read/write happens during Clock Phase 2 (only)
-    if (segs[n->CLK2OUT].on) {
+    if (n->CLK2OUT->on) {
         readBus();
 
-        std::set<int> s;
-        addDataToRecalc(s);
+        std::set<Segment*> s;
+        segs.addDataToRecalc(s);
         recalc(s);
 
         writeBus();
@@ -188,17 +201,3 @@ void Cpu6502::write(unsigned short addr, unsigned char data) {
     std::cout << std::endl;
 #endif
 }
-
-
-
-
-
-
-
-void Cpu6502::recalcAll() {
-    std::set<int> riSeg;
-    for (int iSeg = 0; iSeg < segs.size(); ++iSeg) {
-        addRecalc(iSeg,riSeg);
-    }
-    recalc(riSeg);
-}

Cpu6502.h

@@ -8,6 +8,9 @@
 #ifndef CPU6502_H
 #define	CPU6502_H
 
+#include "TransNetwork.h"
+
+
 class TransNetwork;
 class AddressBus;
 class Trace;
@@ -15,7 +18,7 @@ class Trace;
 class Cpu6502 {
 public:
 
-    Cpu6502(TransNetwork& transNetwork, AddressBus& addressBus, Trace& trace) : transNetwork(transNetwork), addressBus(addressBus), trace(trace) {
+    Cpu6502(TransNetwork& transNetwork, AddressBus& addressBus, Trace& trace) : transNetwork(transNetwork), addressBus(addressBus), trace(trace), segs(transNetwork.segs), n(segs.c) {
     }
 
     virtual ~Cpu6502() {
@@ -37,10 +40,17 @@ private:
     unsigned char read(unsigned short addr);
     void write(unsigned short addr, unsigned char data);
 
+    static void setSeg(Segment* s, bool on);
+    void recalc(Segment* s);
+    void recalc(std::set<Segment*> s);
+
     TransNetwork& transNetwork;
     AddressBus& addressBus;
 
     Trace& trace;
+
+    SegmentCache& segs;
+    SegmentCache::Common* n;
 };
 
 #endif	/* CPU6502_H */

SegmentCache.h

@@ -26,6 +26,14 @@ public:
     Segment* getOrAdd(const std::string& id);
     Segment* get(const std::string& id) const;
 
+    std::set<Segment*> all() {
+        std::set<Segment*> s;
+        for (std::map<const std::string, std::shared_ptr<Segment > >::const_iterator i = cache.begin(); i != cache.end(); ++i) {
+            s.insert(i->second.get());
+        }
+        return s;
+    }
+
     class Common {
     public:
         Segment* VSS;

v6502.cpp

@@ -14,6 +14,7 @@
 
 #include "Cpu6502.h"
 #include "TransNetwork.h"
+#include "Trace.h"
 
 //memory[0xFF] = 0x68;  // PLA
 
@@ -45,8 +46,9 @@ int main(int argc, char *argv[]) {
         exit(EXIT_FAILURE);
     }
     TransNetwork tn(if_trans);
-
-    Cpu6502 cpu(tn);
+    AddressBus mem;
+    Trace trace(tn.segs);
+    Cpu6502 cpu(tn,mem,trace);
 }
 
 int xxxmain(int argc, char *argv[]) {