diff --git a/Makefile b/Makefile
index 34df417..5071964 100644
--- a/Makefile
+++ b/Makefile
@@ -2,13 +2,15 @@ CXXFLAGS=-g
 
 all: v6502
 
-v6502: v6502.o cpu.o
+v6502: v6502.o cpu.o nodes.o
 	g++ $^ -o $@
 
 v6502.o: v6502.cpp cpu.h addressbus.h
 
 cpu.o: cpu.cpp cpu.h addressbus.h nodes.h
 
+nodes.o: nodes.cpp nodes.h
+
 clean:
 	-rm *.o
 	-rm v6502
diff --git a/cpu.cpp b/cpu.cpp
index 4a3ae9e..91a01ae 100644
--- a/cpu.cpp
+++ b/cpu.cpp
@@ -3,6 +3,7 @@
 #include <algorithm>
 #include <utility>
 #include <iterator>
+#include <string>
 #include <vector>
 #include <set>
 #include <map>
@@ -51,78 +52,190 @@ static void pHexw(const unsigned short x) {
 
 
 
+/* power */
+#define VCC sg->isegVCC
+#define VSS sg->isegVSS
+
+/* inputs */
+#define CLK0 sg->isegCLK0
+#define IRQ sg->isegIRQ
+#define RES sg->isegRES
+#define NMI sg->isegNMI
+#define RDY sg->isegRDY
+#define SO sg->isegSO
+
+/* data bus (I/O) */
+#define DB0 sg->isegDB0
+#define DB1 sg->isegDB1
+#define DB3 sg->isegDB3
+#define DB2 sg->isegDB2
+#define DB5 sg->isegDB5
+#define DB4 sg->isegDB4
+#define DB7 sg->isegDB7
+#define DB6 sg->isegDB6
+
+/* address bus (output) */
+#define AB0 sg->isegAB0
+#define AB1 sg->isegAB1
+#define AB2 sg->isegAB2
+#define AB3 sg->isegAB3
+#define AB4 sg->isegAB4
+#define AB5 sg->isegAB5
+#define AB6 sg->isegAB6
+#define AB7 sg->isegAB7
+#define AB8 sg->isegAB8
+#define AB9 sg->isegAB9
+#define AB12 sg->isegAB12
+#define AB13 sg->isegAB13
+#define AB10 sg->isegAB10
+#define AB11 sg->isegAB11
+#define AB14 sg->isegAB14
+#define AB15 sg->isegAB15
+
+/* outputs */
+#define RW sg->isegRW
+#define SYNC sg->isegSYNC
+#define CLK1OUT sg->isegCLK1OUT
+#define CLK2OUT sg->isegCLK2OUT
+
+/* internal registers */
+#define A0 sg->isegA0
+#define A1 sg->isegA1
+#define A2 sg->isegA2
+#define A3 sg->isegA3
+#define A4 sg->isegA4
+#define A5 sg->isegA5
+#define A6 sg->isegA6
+#define A7 sg->isegA7
+
+#define X0 sg->isegX0
+#define X1 sg->isegX1
+#define X2 sg->isegX2
+#define X3 sg->isegX3
+#define X4 sg->isegX4
+#define X5 sg->isegX5
+#define X6 sg->isegX6
+#define X7 sg->isegX7
+
+#define Y0 sg->isegY0
+#define Y1 sg->isegY1
+#define Y2 sg->isegY2
+#define Y3 sg->isegY3
+#define Y4 sg->isegY4
+#define Y5 sg->isegY5
+#define Y6 sg->isegY6
+#define Y7 sg->isegY7
+
+#define PCL0 sg->isegPCL0
+#define PCL1 sg->isegPCL1
+#define PCL2 sg->isegPCL2
+#define PCL3 sg->isegPCL3
+#define PCL4 sg->isegPCL4
+#define PCL5 sg->isegPCL5
+#define PCL6 sg->isegPCL6
+#define PCL7 sg->isegPCL7
+
+#define PCH0 sg->isegPCH0
+#define PCH1 sg->isegPCH1
+#define PCH2 sg->isegPCH2
+#define PCH3 sg->isegPCH3
+#define PCH4 sg->isegPCH4
+#define PCH5 sg->isegPCH5
+#define PCH6 sg->isegPCH6
+#define PCH7 sg->isegPCH7
+
+#define P0 sg->isegP0
+#define P1 sg->isegP1
+#define P2 sg->isegP2
+#define P3 sg->isegP3
+#define P4 sg->isegP4
+#define P6 sg->isegP6
+#define P7 sg->isegP7
+
+#define S0 sg->isegS0
+#define S1 sg->isegS1
+#define S2 sg->isegS2
+#define S3 sg->isegS3
+#define S4 sg->isegS4
+#define S5 sg->isegS5
+#define S6 sg->isegS6
+#define S7 sg->isegS7
+
+
+
+static nodes* sg;
+
+static std::map<int,std::string> map_i_seg;
+
+static int get_i_seg(const std::string& seg, std::map<std::string,int>& map_seg_i) {
+    static int i_segin(0);
+    int i_seg = -1;
+    if (map_seg_i.find(seg) == map_seg_i.end()) {
+        i_seg = i_segin++;
+        map_seg_i[seg] = i_seg;
+        map_i_seg[i_seg] = seg;
+    } else {
+        i_seg = map_seg_i[seg];
+    }
+    return i_seg;
+}
+
 CPU::CPU(AddressBus& addressBus) :
 addressBus(addressBus) {
-    std::cout << "reading segsonly";
-    std::ifstream if_segs("segsonly");
-    if (!if_segs.is_open()) {
-        std::cerr << "error opening file: segs" << std::endl;
+    std::cout << "reading transistors";
+    std::ifstream if_trans("transistors");
+    if (!if_trans.is_open()) {
+        std::cerr << "error opening file: transistors" << std::endl;
         exit(EXIT_FAILURE);
     }
 
-    int i_seg(0);
-    while (if_segs.good()) {
-        int i_segin(-1);
-        bool b_on(false);
-        if_segs >> i_segin >> b_on;
-        if (i_segin >= 0) {
-            if (i_segin != i_seg++) {
-                std::cerr << "error: mismatch in segsonly file near " << i_segin << std::endl;
-                exit(EXIT_FAILURE);
-            }
-            std::cout << ".";
-            seg s;
-            s.pullup = b_on;
-            s.pulldown = false;
-            s.on = false;
-            segs.push_back(s);
-        }
-    }
-    std::cout << std::endl << "read " << segs.size() << " segs" << std::endl;
-
-
-
-    std::cout << "reading trns";
-    std::ifstream if_trns("trns");
-    if (!if_trns.is_open()) {
-        std::cerr << "error opening file: trns" << std::endl;
-        exit(EXIT_FAILURE);
-    }
-
-    int i_trn(0);
-    while (if_trns.good()) {
+    std::string seg_c1, seg_gate, seg_c2;
+    if_trans >> seg_c1 >> seg_gate >> seg_c2;
+    while (if_trans.good()) {
         std::cout << ".";
-        int i_trnin(-1);
-        int i_gate, i_c1, i_c2;
-        if_trns >> i_trnin >> i_gate >> i_c1 >> i_c2;
-        if (i_trnin >= 0) {
-            if (i_trnin != i_trn++) {
-                std::cerr << "error: mismatch in trns file near " << i_trnin << std::endl;
-                exit(EXIT_FAILURE);
-            }
-            trn t;
-            t.gate = i_gate;
-            t.c1 = i_c1;
-            t.c2 = i_c2;
-            t.on = false;
-            trns.push_back(t);
-        }
-    }
-    std::cout << std::endl << "read " << trns.size() << " trns" << std::endl;
 
+        trn t;
+        t.on = false;
+        t.c1 = get_i_seg(seg_c1,map_seg_i);
+        t.gate = get_i_seg(seg_gate,map_seg_i);
+        t.c2 = get_i_seg(seg_c2,map_seg_i);
+        trns.push_back(t);
+
+        if_trans >> seg_c1 >> seg_gate >> seg_c2;
+    }
+    std::cout << std::endl << "read " << map_seg_i.size() << " segments, " << trns.size() << " transistors" << std::endl;
+
+    for (int i_seg = 0; i_seg < map_seg_i.size(); ++i_seg)
+    {
+        const std::string id_seg = map_i_seg[i_seg];
+
+        seg s;
+        s.id = id_seg;
+        s.pullup = id_seg[0] == '+';
+        s.pulldown = false;
+        s.on = false;
+        segs.push_back(s);
+    }
+
+
+
+    const int isegVSS = map_seg_i["-vss"];
+    const int isegVCC = map_seg_i["-vcc"];
     for (int i = 0; i != trns.size(); ++i) {
         trn& t = trns[i];
-        if (t.c1 == VSS) {
+        if (t.c1 == isegVSS) {
             t.c1 = t.c2;
-            t.c2 = VSS;
-        } else if (t.c1 == VCC) {
+            t.c2 = isegVSS;
+        } else if (t.c1 == isegVCC) {
             t.c1 = t.c2;
-            t.c2 = VCC;
+            t.c2 = isegVCC;
         }
         segs[t.gate].gates.push_back(i);
         segs[t.c1].c1c2s.push_back(i);
         segs[t.c2].c1c2s.push_back(i);
     }
+
+    sg = new nodes(map_seg_i);
 }
 
 CPU::~CPU() {
diff --git a/cpu.h b/cpu.h
index f3edba6..efedf6c 100644
--- a/cpu.h
+++ b/cpu.h
@@ -1,13 +1,16 @@
 #ifndef CPU_H
 #define CPU_H
 
+#include <string>
 #include <vector>
 #include <set>
+#include <map>
 
 class AddressBus;
 
 class seg {
 public:
+    std::string id;
     bool pullup;
     bool pulldown;
     bool on;
@@ -25,6 +28,7 @@ public:
 
 class CPU {
 private:
+    std::map<std::string,int> map_seg_i;
     std::vector<seg> segs;
     std::vector<trn> trns;
     AddressBus& addressBus;
diff --git a/nodes.cpp b/nodes.cpp
new file mode 100644
index 0000000..ba14d9a
--- /dev/null
+++ b/nodes.cpp
@@ -0,0 +1,115 @@
+#include "nodes.h"
+#include <string>
+#include <map>
+
+nodes::nodes(std::map<std::string,int>& map_seg_i) {
+/* power */
+    isegVCC = map_seg_i["-vcc"];
+    isegVSS = map_seg_i["-vss"];
+
+/* inputs */
+    isegCLK0 = map_seg_i["-clk0"];
+    isegIRQ = map_seg_i["-irq"];
+    isegRES = map_seg_i["-res"];
+    isegNMI = map_seg_i["-nmi"];
+    isegRDY = map_seg_i["+rdy"];
+    isegSO = map_seg_i["+s0"];
+
+/* data bus (I/O) */
+    isegDB0 = map_seg_i["-db0"];
+    isegDB1 = map_seg_i["-db1"];
+    isegDB2 = map_seg_i["-db2"];
+    isegDB3 = map_seg_i["-db3"];
+    isegDB4 = map_seg_i["-db4"];
+    isegDB5 = map_seg_i["-db5"];
+    isegDB6 = map_seg_i["-db6"];
+    isegDB7 = map_seg_i["-db7"];
+
+/* address bus (output) */
+    isegAB0 = map_seg_i["-ab0"];
+    isegAB1 = map_seg_i["-ab1"];
+    isegAB2 = map_seg_i["-ab2"];
+    isegAB3 = map_seg_i["-ab3"];
+    isegAB4 = map_seg_i["-ab4"];
+    isegAB5 = map_seg_i["-ab5"];
+    isegAB6 = map_seg_i["-ab6"];
+    isegAB7 = map_seg_i["-ab7"];
+    isegAB8 = map_seg_i["-ab8"];
+    isegAB9 = map_seg_i["-ab9"];
+    isegAB10 = map_seg_i["-ab10"];
+    isegAB11 = map_seg_i["-ab11"];
+    isegAB12 = map_seg_i["-ab12"];
+    isegAB13 = map_seg_i["-ab13"];
+    isegAB14 = map_seg_i["-ab14"];
+    isegAB15 = map_seg_i["-ab15"];
+
+/* outputs */
+    isegRW = map_seg_i["-rw"];
+    isegSYNC = map_seg_i["-sync"];
+    isegCLK1OUT = map_seg_i["-clk1out"];
+    isegCLK2OUT = map_seg_i["-clk2out"];
+
+/* internal registers */
+    isegA0 = map_seg_i["-a0"];
+    isegA1 = map_seg_i["-a1"];
+    isegA2 = map_seg_i["-a2"];
+    isegA3 = map_seg_i["-a3"];
+    isegA4 = map_seg_i["-a4"];
+    isegA5 = map_seg_i["-a5"];
+    isegA6 = map_seg_i["-a6"];
+    isegA7 = map_seg_i["-a7"];
+
+    isegX0 = map_seg_i["-x0"];
+    isegX1 = map_seg_i["-x1"];
+    isegX2 = map_seg_i["-x2"];
+    isegX3 = map_seg_i["-x3"];
+    isegX4 = map_seg_i["-x4"];
+    isegX5 = map_seg_i["-x5"];
+    isegX6 = map_seg_i["-x6"];
+    isegX7 = map_seg_i["-x7"];
+
+    isegY0 = map_seg_i["-y0"];
+    isegY1 = map_seg_i["-y1"];
+    isegY2 = map_seg_i["-y2"];
+    isegY3 = map_seg_i["-y3"];
+    isegY4 = map_seg_i["-y4"];
+    isegY5 = map_seg_i["-y5"];
+    isegY6 = map_seg_i["-y6"];
+    isegY7 = map_seg_i["-y7"];
+
+    isegPCL0 = map_seg_i["-pcl0"];
+    isegPCL1 = map_seg_i["-pcl1"];
+    isegPCL2 = map_seg_i["-pcl2"];
+    isegPCL3 = map_seg_i["-pcl3"];
+    isegPCL4 = map_seg_i["-pcl4"];
+    isegPCL5 = map_seg_i["-pcl5"];
+    isegPCL6 = map_seg_i["-pcl6"];
+    isegPCL7 = map_seg_i["-pcl7"];
+
+    isegPCH0 = map_seg_i["-pch0"];
+    isegPCH1 = map_seg_i["-pch1"];
+    isegPCH2 = map_seg_i["-pch2"];
+    isegPCH3 = map_seg_i["-pch3"];
+    isegPCH4 = map_seg_i["-pch4"];
+    isegPCH5 = map_seg_i["-pch5"];
+    isegPCH6 = map_seg_i["-pch6"];
+    isegPCH7 = map_seg_i["-pch7"];
+
+    isegP0 = map_seg_i["+Pout0"];
+    isegP1 = map_seg_i["+Pout1"];
+    isegP2 = map_seg_i["+Pout2"];
+    isegP3 = map_seg_i["+Pout3"];
+    isegP4 = map_seg_i["+Pout4"];
+    // P5 does not exist in the 6502 chip
+    isegP6 = map_seg_i["+Pout6"];
+    isegP7 = map_seg_i["+Pout7"];
+
+    isegS0 = map_seg_i["-s0"];
+    isegS1 = map_seg_i["-s1"];
+    isegS2 = map_seg_i["-s2"];
+    isegS3 = map_seg_i["-s3"];
+    isegS4 = map_seg_i["-s4"];
+    isegS5 = map_seg_i["-s5"];
+    isegS6 = map_seg_i["-s6"];
+    isegS7 = map_seg_i["-s7"];
+}
diff --git a/nodes.h b/nodes.h
index d99d5cb..3b75ab8 100644
--- a/nodes.h
+++ b/nodes.h
@@ -1,108 +1,121 @@
+#ifndef NODES_H
+#define NODES_H
+
+#include <string>
+#include <map>
+
+class nodes {
+public:
 /* power */
-#define VCC (657)
-#define VSS (558)
+    int isegVCC;
+    int isegVSS;
 
 /* inputs */
-#define CLK0 (1171)
-#define IRQ (103)
-#define RES (159)
-#define NMI (1297)
-#define RDY (89)
-#define SO (1672)
+    int isegCLK0;
+    int isegIRQ;
+    int isegRES;
+    int isegNMI;
+    int isegRDY;
+    int isegSO;
 
-/* data bus (I/O) */
-#define DB0 (1005)
-#define DB1 (82)
-#define DB3 (650)
-#define DB2 (945)
-#define DB5 (175)
-#define DB4 (1393)
-#define DB7 (1349)
-#define DB6 (1591)
+/* data bus; */
+    int isegDB0;
+    int isegDB1;
+    int isegDB3;
+    int isegDB2;
+    int isegDB5;
+    int isegDB4;
+    int isegDB7;
+    int isegDB6;
 
-/* address bus (output) */
-#define AB0 (268)
-#define AB1 (451)
-#define AB2 (1340)
-#define AB3 (211)
-#define AB4 (435)
-#define AB5 (736)
-#define AB6 (887)
-#define AB7 (1493)
-#define AB8 (230)
-#define AB9 (148)
-#define AB12 (1237)
-#define AB13 (349)
-#define AB10 (1443)
-#define AB11 (399)
-#define AB14 (672)
-#define AB15 (195)
+/* address bus; */
+    int isegAB0;
+    int isegAB1;
+    int isegAB2;
+    int isegAB3;
+    int isegAB4;
+    int isegAB5;
+    int isegAB6;
+    int isegAB7;
+    int isegAB8;
+    int isegAB9;
+    int isegAB12;
+    int isegAB13;
+    int isegAB10;
+    int isegAB11;
+    int isegAB14;
+    int isegAB15;
 
 /* outputs */
-#define RW (1156)
-#define SYNC (539)
-#define CLK1OUT (1163)
-#define CLK2OUT (421)
+    int isegRW;
+    int isegSYNC;
+    int isegCLK1OUT;
+    int isegCLK2OUT;
 
 /* internal registers */
-#define A0 (737)
-#define A1 (1234)
-#define A2 (978)
-#define A3 (162)
-#define A4 (727)
-#define A5 (858)
-#define A6 (1136)
-#define A7 (1653)
+    int isegA0;
+    int isegA1;
+    int isegA2;
+    int isegA3;
+    int isegA4;
+    int isegA5;
+    int isegA6;
+    int isegA7;
 
-#define X0 (1216)
-#define X1 (98)
-#define X2 (1)
-#define X3 (1648)
-#define X4 (85)
-#define X5 (589)
-#define X6 (448)
-#define X7 (777)
+    int isegX0;
+    int isegX1;
+    int isegX2;
+    int isegX3;
+    int isegX4;
+    int isegX5;
+    int isegX6;
+    int isegX7;
 
-#define Y0 (64)
-#define Y1 (1148)
-#define Y2 (573)
-#define Y3 (305)
-#define Y4 (989)
-#define Y5 (615)
-#define Y6 (115)
-#define Y7 (843)
+    int isegY0;
+    int isegY1;
+    int isegY2;
+    int isegY3;
+    int isegY4;
+    int isegY5;
+    int isegY6;
+    int isegY7;
 
-#define PCL0 (1139)
-#define PCL1 (1022)
-#define PCL2 (655)
-#define PCL3 (1359)
-#define PCL4 (900)
-#define PCL5 (622)
-#define PCL6 (377)
-#define PCL7 (1611)
+    int isegPCL0;
+    int isegPCL1;
+    int isegPCL2;
+    int isegPCL3;
+    int isegPCL4;
+    int isegPCL5;
+    int isegPCL6;
+    int isegPCL7;
 
-#define PCH0 (1670)
-#define PCH1 (292)
-#define PCH2 (502)
-#define PCH3 (584)
-#define PCH4 (948)
-#define PCH5 (49)
-#define PCH6 (1551)
-#define PCH7 (205)
+    int isegPCH0;
+    int isegPCH1;
+    int isegPCH2;
+    int isegPCH3;
+    int isegPCH4;
+    int isegPCH5;
+    int isegPCH6;
+    int isegPCH7;
 
-#define P0 (32)
-#define P1 (627)
-#define P2 (1553)
-#define P3 (348)
-#define P4 (1119)
-#define P6 (77)
-#define P7 (1370)
+    int isegP0;
+    int isegP1;
+    int isegP2;
+    int isegP3;
+    int isegP4;
+    int isegP6;
+    int isegP7;
 
-#define S0 (1403)
-#define S1 (183)
-#define S2 (81)
-#define S3 (1532)
-#define S4 (1702)
-#define S5 (1098)
-#define S6 (1212)
-#define S7 (1435)
+    int isegS0;
+    int isegS1;
+    int isegS2;
+    int isegS3;
+    int isegS4;
+    int isegS5;
+    int isegS6;
+    int isegS7;
+
+    nodes(std::map<std::string,int>& map_seg_i);
+};
+
+#endif
diff --git a/segs b/segs
deleted file mode 100644
index c488f2a..0000000
--- a/segs
+++ /dev/null
@@ -1,1725 +0,0 @@
-0 1
-1 0
-2 0
-3 1
-4 1
-5 1
-6 1
-7 0
-8 1
-9 0
-10 1
-11 1
-12 0
-13 0
-14 1
-15 0
-16 1
-17 1
-18 0
-19 1
-20 1
-21 1
-22 1
-23 1
-24 0
-25 1
-26 1
-27 1
-28 0
-29 1
-
-31 1
-32 0
-33 1
-34 1
-35 1
-36 1
-37 0
-38 1
-39 1
-40 0
-41 0
-42 0
-43 0
-44 0
-45 0
-46 1
-47 0
-48 0
-49 0
-50 0
-51 0
-52 0
-53 1
-54 0
-55 0
-56 0
-57 0
-58 1
-59 0
-60 1
-61 1
-62 1
-63 1
-64 0
-65 1
-66 0
-67 1
-68 0
-69 0
-70 1
-71 1
-72 1
-73 0
-74 0
-75 1
-76 1
-77 1
-78 1
-79 1
-80 1
-81 0
-82 0
-83 1
-84 1
-85 0
-86 0
-87 0
-88 0
-89 1
-90 1
-91 1
-92 0
-93 1
-94 0
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diff --git a/segsonly b/segsonly
deleted file mode 100755
index 4c508c1..0000000
--- a/segsonly
+++ /dev/null
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diff --git a/newtrans b/transistors
similarity index 100%
rename from newtrans
rename to transistors
diff --git a/trns b/trns
deleted file mode 100644
index 2f635ab..0000000
--- a/trns
+++ /dev/null
@@ -1,3510 +0,0 @@
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