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v6502cpp
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incorporate new transistor format file into code

This commit is contained in:
Christopher Mosher 2013-12-09 19:17:26 -05:00
parent 7bd00764c2
commit 9b0bc1bb15
9 changed files with 397 additions and 7110 deletions
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4
Makefile
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@ -2,13 +2,15 @@ CXXFLAGS=-g
all: v6502 all: v6502
v6502: v6502.o cpu.o v6502: v6502.o cpu.o nodes.o
g++ $^ -o $@ g++ $^ -o $@
v6502.o: v6502.cpp cpu.h addressbus.h v6502.o: v6502.cpp cpu.h addressbus.h
cpu.o: cpu.cpp cpu.h addressbus.h nodes.h cpu.o: cpu.cpp cpu.h addressbus.h nodes.h
nodes.o: nodes.cpp nodes.h
clean: clean:
-rm *.o -rm *.o
-rm v6502 -rm v6502

225
cpu.cpp
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@ -3,6 +3,7 @@
#include <algorithm> #include <algorithm>
#include <utility> #include <utility>
#include <iterator> #include <iterator>
#include <string>
#include <vector> #include <vector>
#include <set> #include <set>
#include <map> #include <map>
@ -51,78 +52,190 @@ static void pHexw(const unsigned short x) {
/* power */
#define VCC sg->isegVCC
#define VSS sg->isegVSS
/* inputs */
#define CLK0 sg->isegCLK0
#define IRQ sg->isegIRQ
#define RES sg->isegRES
#define NMI sg->isegNMI
#define RDY sg->isegRDY
#define SO sg->isegSO
/* data bus (I/O) */
#define DB0 sg->isegDB0
#define DB1 sg->isegDB1
#define DB3 sg->isegDB3
#define DB2 sg->isegDB2
#define DB5 sg->isegDB5
#define DB4 sg->isegDB4
#define DB7 sg->isegDB7
#define DB6 sg->isegDB6
/* address bus (output) */
#define AB0 sg->isegAB0
#define AB1 sg->isegAB1
#define AB2 sg->isegAB2
#define AB3 sg->isegAB3
#define AB4 sg->isegAB4
#define AB5 sg->isegAB5
#define AB6 sg->isegAB6
#define AB7 sg->isegAB7
#define AB8 sg->isegAB8
#define AB9 sg->isegAB9
#define AB12 sg->isegAB12
#define AB13 sg->isegAB13
#define AB10 sg->isegAB10
#define AB11 sg->isegAB11
#define AB14 sg->isegAB14
#define AB15 sg->isegAB15
/* outputs */
#define RW sg->isegRW
#define SYNC sg->isegSYNC
#define CLK1OUT sg->isegCLK1OUT
#define CLK2OUT sg->isegCLK2OUT
/* internal registers */
#define A0 sg->isegA0
#define A1 sg->isegA1
#define A2 sg->isegA2
#define A3 sg->isegA3
#define A4 sg->isegA4
#define A5 sg->isegA5
#define A6 sg->isegA6
#define A7 sg->isegA7
#define X0 sg->isegX0
#define X1 sg->isegX1
#define X2 sg->isegX2
#define X3 sg->isegX3
#define X4 sg->isegX4
#define X5 sg->isegX5
#define X6 sg->isegX6
#define X7 sg->isegX7
#define Y0 sg->isegY0
#define Y1 sg->isegY1
#define Y2 sg->isegY2
#define Y3 sg->isegY3
#define Y4 sg->isegY4
#define Y5 sg->isegY5
#define Y6 sg->isegY6
#define Y7 sg->isegY7
#define PCL0 sg->isegPCL0
#define PCL1 sg->isegPCL1
#define PCL2 sg->isegPCL2
#define PCL3 sg->isegPCL3
#define PCL4 sg->isegPCL4
#define PCL5 sg->isegPCL5
#define PCL6 sg->isegPCL6
#define PCL7 sg->isegPCL7
#define PCH0 sg->isegPCH0
#define PCH1 sg->isegPCH1
#define PCH2 sg->isegPCH2
#define PCH3 sg->isegPCH3
#define PCH4 sg->isegPCH4
#define PCH5 sg->isegPCH5
#define PCH6 sg->isegPCH6
#define PCH7 sg->isegPCH7
#define P0 sg->isegP0
#define P1 sg->isegP1
#define P2 sg->isegP2
#define P3 sg->isegP3
#define P4 sg->isegP4
#define P6 sg->isegP6
#define P7 sg->isegP7
#define S0 sg->isegS0
#define S1 sg->isegS1
#define S2 sg->isegS2
#define S3 sg->isegS3
#define S4 sg->isegS4
#define S5 sg->isegS5
#define S6 sg->isegS6
#define S7 sg->isegS7
static nodes* sg;
static std::map<int,std::string> map_i_seg;
static int get_i_seg(const std::string& seg, std::map<std::string,int>& map_seg_i) {
static int i_segin(0);
int i_seg = -1;
if (map_seg_i.find(seg) == map_seg_i.end()) {
i_seg = i_segin++;
map_seg_i[seg] = i_seg;
map_i_seg[i_seg] = seg;
} else {
i_seg = map_seg_i[seg];
}
return i_seg;
}
CPU::CPU(AddressBus& addressBus) : CPU::CPU(AddressBus& addressBus) :
addressBus(addressBus) { addressBus(addressBus) {
std::cout << "reading segsonly"; std::cout << "reading transistors";
std::ifstream if_segs("segsonly"); std::ifstream if_trans("transistors");
if (!if_segs.is_open()) { if (!if_trans.is_open()) {
std::cerr << "error opening file: segs" << std::endl; std::cerr << "error opening file: transistors" << std::endl;
exit(EXIT_FAILURE); exit(EXIT_FAILURE);
} }
int i_seg(0); std::string seg_c1, seg_gate, seg_c2;
while (if_segs.good()) { if_trans >> seg_c1 >> seg_gate >> seg_c2;
int i_segin(-1); while (if_trans.good()) {
bool b_on(false);
if_segs >> i_segin >> b_on;
if (i_segin >= 0) {
if (i_segin != i_seg++) {
std::cerr << "error: mismatch in segsonly file near " << i_segin << std::endl;
exit(EXIT_FAILURE);
}
std::cout << ".";
seg s;
s.pullup = b_on;
s.pulldown = false;
s.on = false;
segs.push_back(s);
}
}
std::cout << std::endl << "read " << segs.size() << " segs" << std::endl;
std::cout << "reading trns";
std::ifstream if_trns("trns");
if (!if_trns.is_open()) {
std::cerr << "error opening file: trns" << std::endl;
exit(EXIT_FAILURE);
}
int i_trn(0);
while (if_trns.good()) {
std::cout << "."; std::cout << ".";
int i_trnin(-1);
int i_gate, i_c1, i_c2;
if_trns >> i_trnin >> i_gate >> i_c1 >> i_c2;
if (i_trnin >= 0) {
if (i_trnin != i_trn++) {
std::cerr << "error: mismatch in trns file near " << i_trnin << std::endl;
exit(EXIT_FAILURE);
}
trn t;
t.gate = i_gate;
t.c1 = i_c1;
t.c2 = i_c2;
t.on = false;
trns.push_back(t);
}
}
std::cout << std::endl << "read " << trns.size() << " trns" << std::endl;
trn t;
t.on = false;
t.c1 = get_i_seg(seg_c1,map_seg_i);
t.gate = get_i_seg(seg_gate,map_seg_i);
t.c2 = get_i_seg(seg_c2,map_seg_i);
trns.push_back(t);
if_trans >> seg_c1 >> seg_gate >> seg_c2;
}
std::cout << std::endl << "read " << map_seg_i.size() << " segments, " << trns.size() << " transistors" << std::endl;
for (int i_seg = 0; i_seg < map_seg_i.size(); ++i_seg)
{
const std::string id_seg = map_i_seg[i_seg];
seg s;
s.id = id_seg;
s.pullup = id_seg[0] == '+';
s.pulldown = false;
s.on = false;
segs.push_back(s);
}
const int isegVSS = map_seg_i["-vss"];
const int isegVCC = map_seg_i["-vcc"];
for (int i = 0; i != trns.size(); ++i) { for (int i = 0; i != trns.size(); ++i) {
trn& t = trns[i]; trn& t = trns[i];
if (t.c1 == VSS) { if (t.c1 == isegVSS) {
t.c1 = t.c2; t.c1 = t.c2;
t.c2 = VSS; t.c2 = isegVSS;
} else if (t.c1 == VCC) { } else if (t.c1 == isegVCC) {
t.c1 = t.c2; t.c1 = t.c2;
t.c2 = VCC; t.c2 = isegVCC;
} }
segs[t.gate].gates.push_back(i); segs[t.gate].gates.push_back(i);
segs[t.c1].c1c2s.push_back(i); segs[t.c1].c1c2s.push_back(i);
segs[t.c2].c1c2s.push_back(i); segs[t.c2].c1c2s.push_back(i);
} }
sg = new nodes(map_seg_i);
} }
CPU::~CPU() { CPU::~CPU() {

4
cpu.h
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@ -1,13 +1,16 @@
#ifndef CPU_H #ifndef CPU_H
#define CPU_H #define CPU_H
#include <string>
#include <vector> #include <vector>
#include <set> #include <set>
#include <map>
class AddressBus; class AddressBus;
class seg { class seg {
public: public:
std::string id;
bool pullup; bool pullup;
bool pulldown; bool pulldown;
bool on; bool on;
@ -25,6 +28,7 @@ public:
class CPU { class CPU {
private: private:
std::map<std::string,int> map_seg_i;
std::vector<seg> segs; std::vector<seg> segs;
std::vector<trn> trns; std::vector<trn> trns;
AddressBus& addressBus; AddressBus& addressBus;

115
nodes.cpp Normal file
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@ -0,0 +1,115 @@
#include "nodes.h"
#include <string>
#include <map>
nodes::nodes(std::map<std::string,int>& map_seg_i) {
/* power */
isegVCC = map_seg_i["-vcc"];
isegVSS = map_seg_i["-vss"];
/* inputs */
isegCLK0 = map_seg_i["-clk0"];
isegIRQ = map_seg_i["-irq"];
isegRES = map_seg_i["-res"];
isegNMI = map_seg_i["-nmi"];
isegRDY = map_seg_i["+rdy"];
isegSO = map_seg_i["+s0"];
/* data bus (I/O) */
isegDB0 = map_seg_i["-db0"];
isegDB1 = map_seg_i["-db1"];
isegDB2 = map_seg_i["-db2"];
isegDB3 = map_seg_i["-db3"];
isegDB4 = map_seg_i["-db4"];
isegDB5 = map_seg_i["-db5"];
isegDB6 = map_seg_i["-db6"];
isegDB7 = map_seg_i["-db7"];
/* address bus (output) */
isegAB0 = map_seg_i["-ab0"];
isegAB1 = map_seg_i["-ab1"];
isegAB2 = map_seg_i["-ab2"];
isegAB3 = map_seg_i["-ab3"];
isegAB4 = map_seg_i["-ab4"];
isegAB5 = map_seg_i["-ab5"];
isegAB6 = map_seg_i["-ab6"];
isegAB7 = map_seg_i["-ab7"];
isegAB8 = map_seg_i["-ab8"];
isegAB9 = map_seg_i["-ab9"];
isegAB10 = map_seg_i["-ab10"];
isegAB11 = map_seg_i["-ab11"];
isegAB12 = map_seg_i["-ab12"];
isegAB13 = map_seg_i["-ab13"];
isegAB14 = map_seg_i["-ab14"];
isegAB15 = map_seg_i["-ab15"];
/* outputs */
isegRW = map_seg_i["-rw"];
isegSYNC = map_seg_i["-sync"];
isegCLK1OUT = map_seg_i["-clk1out"];
isegCLK2OUT = map_seg_i["-clk2out"];
/* internal registers */
isegA0 = map_seg_i["-a0"];
isegA1 = map_seg_i["-a1"];
isegA2 = map_seg_i["-a2"];
isegA3 = map_seg_i["-a3"];
isegA4 = map_seg_i["-a4"];
isegA5 = map_seg_i["-a5"];
isegA6 = map_seg_i["-a6"];
isegA7 = map_seg_i["-a7"];
isegX0 = map_seg_i["-x0"];
isegX1 = map_seg_i["-x1"];
isegX2 = map_seg_i["-x2"];
isegX3 = map_seg_i["-x3"];
isegX4 = map_seg_i["-x4"];
isegX5 = map_seg_i["-x5"];
isegX6 = map_seg_i["-x6"];
isegX7 = map_seg_i["-x7"];
isegY0 = map_seg_i["-y0"];
isegY1 = map_seg_i["-y1"];
isegY2 = map_seg_i["-y2"];
isegY3 = map_seg_i["-y3"];
isegY4 = map_seg_i["-y4"];
isegY5 = map_seg_i["-y5"];
isegY6 = map_seg_i["-y6"];
isegY7 = map_seg_i["-y7"];
isegPCL0 = map_seg_i["-pcl0"];
isegPCL1 = map_seg_i["-pcl1"];
isegPCL2 = map_seg_i["-pcl2"];
isegPCL3 = map_seg_i["-pcl3"];
isegPCL4 = map_seg_i["-pcl4"];
isegPCL5 = map_seg_i["-pcl5"];
isegPCL6 = map_seg_i["-pcl6"];
isegPCL7 = map_seg_i["-pcl7"];
isegPCH0 = map_seg_i["-pch0"];
isegPCH1 = map_seg_i["-pch1"];
isegPCH2 = map_seg_i["-pch2"];
isegPCH3 = map_seg_i["-pch3"];
isegPCH4 = map_seg_i["-pch4"];
isegPCH5 = map_seg_i["-pch5"];
isegPCH6 = map_seg_i["-pch6"];
isegPCH7 = map_seg_i["-pch7"];
isegP0 = map_seg_i["+Pout0"];
isegP1 = map_seg_i["+Pout1"];
isegP2 = map_seg_i["+Pout2"];
isegP3 = map_seg_i["+Pout3"];
isegP4 = map_seg_i["+Pout4"];
// P5 does not exist in the 6502 chip
isegP6 = map_seg_i["+Pout6"];
isegP7 = map_seg_i["+Pout7"];
isegS0 = map_seg_i["-s0"];
isegS1 = map_seg_i["-s1"];
isegS2 = map_seg_i["-s2"];
isegS3 = map_seg_i["-s3"];
isegS4 = map_seg_i["-s4"];
isegS5 = map_seg_i["-s5"];
isegS6 = map_seg_i["-s6"];
isegS7 = map_seg_i["-s7"];
}

199
nodes.h
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@ -1,108 +1,121 @@
#ifndef NODES_H
#define NODES_H
#include <string>
#include <map>
class nodes {
public:
/* power */ /* power */
#define VCC (657) int isegVCC;
#define VSS (558) int isegVSS;
/* inputs */ /* inputs */
#define CLK0 (1171) int isegCLK0;
#define IRQ (103) int isegIRQ;
#define RES (159) int isegRES;
#define NMI (1297) int isegNMI;
#define RDY (89) int isegRDY;
#define SO (1672) int isegSO;
/* data bus (I/O) */ /* data bus; */
#define DB0 (1005) int isegDB0;
#define DB1 (82) int isegDB1;
#define DB3 (650) int isegDB3;
#define DB2 (945) int isegDB2;
#define DB5 (175) int isegDB5;
#define DB4 (1393) int isegDB4;
#define DB7 (1349) int isegDB7;
#define DB6 (1591) int isegDB6;
/* address bus (output) */ /* address bus; */
#define AB0 (268) int isegAB0;
#define AB1 (451) int isegAB1;
#define AB2 (1340) int isegAB2;
#define AB3 (211) int isegAB3;
#define AB4 (435) int isegAB4;
#define AB5 (736) int isegAB5;
#define AB6 (887) int isegAB6;
#define AB7 (1493) int isegAB7;
#define AB8 (230) int isegAB8;
#define AB9 (148) int isegAB9;
#define AB12 (1237) int isegAB12;
#define AB13 (349) int isegAB13;
#define AB10 (1443) int isegAB10;
#define AB11 (399) int isegAB11;
#define AB14 (672) int isegAB14;
#define AB15 (195) int isegAB15;
/* outputs */ /* outputs */
#define RW (1156) int isegRW;
#define SYNC (539) int isegSYNC;
#define CLK1OUT (1163) int isegCLK1OUT;
#define CLK2OUT (421) int isegCLK2OUT;
/* internal registers */ /* internal registers */
#define A0 (737) int isegA0;
#define A1 (1234) int isegA1;
#define A2 (978) int isegA2;
#define A3 (162) int isegA3;
#define A4 (727) int isegA4;
#define A5 (858) int isegA5;
#define A6 (1136) int isegA6;
#define A7 (1653) int isegA7;
#define X0 (1216) int isegX0;
#define X1 (98) int isegX1;
#define X2 (1) int isegX2;
#define X3 (1648) int isegX3;
#define X4 (85) int isegX4;
#define X5 (589) int isegX5;
#define X6 (448) int isegX6;
#define X7 (777) int isegX7;
#define Y0 (64) int isegY0;
#define Y1 (1148) int isegY1;
#define Y2 (573) int isegY2;
#define Y3 (305) int isegY3;
#define Y4 (989) int isegY4;
#define Y5 (615) int isegY5;
#define Y6 (115) int isegY6;
#define Y7 (843) int isegY7;
#define PCL0 (1139) int isegPCL0;
#define PCL1 (1022) int isegPCL1;
#define PCL2 (655) int isegPCL2;
#define PCL3 (1359) int isegPCL3;
#define PCL4 (900) int isegPCL4;
#define PCL5 (622) int isegPCL5;
#define PCL6 (377) int isegPCL6;
#define PCL7 (1611) int isegPCL7;
#define PCH0 (1670) int isegPCH0;
#define PCH1 (292) int isegPCH1;
#define PCH2 (502) int isegPCH2;
#define PCH3 (584) int isegPCH3;
#define PCH4 (948) int isegPCH4;
#define PCH5 (49) int isegPCH5;
#define PCH6 (1551) int isegPCH6;
#define PCH7 (205) int isegPCH7;
#define P0 (32) int isegP0;
#define P1 (627) int isegP1;
#define P2 (1553) int isegP2;
#define P3 (348) int isegP3;
#define P4 (1119) int isegP4;
#define P6 (77) int isegP6;
#define P7 (1370) int isegP7;
#define S0 (1403) int isegS0;
#define S1 (183) int isegS1;
#define S2 (81) int isegS2;
#define S3 (1532) int isegS3;
#define S4 (1702) int isegS4;
#define S5 (1098) int isegS5;
#define S6 (1212) int isegS6;
#define S7 (1435) int isegS7;
nodes(std::map<std::string,int>& map_seg_i);
};
#endif

1725
segs
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File diff suppressed because it is too large Load Diff

1725
segsonly
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File diff suppressed because it is too large Load Diff

0
newtrans → transistors
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3510
trns
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File diff suppressed because it is too large Load Diff