From b5446cca3f0997bc7a3ee2170b090706c0791255 Mon Sep 17 00:00:00 2001 From: Christopher Mosher Date: Tue, 10 Dec 2013 13:25:14 -0500 Subject: [PATCH] refactor: remove iseg prefix from segment constants --- cpu.cpp | 236 ++++++++++++++---------------------------------------- nodes.cpp | 182 ++++++++++++++++++++--------------------- nodes.h | 182 ++++++++++++++++++++--------------------- 3 files changed, 243 insertions(+), 357 deletions(-) diff --git a/cpu.cpp b/cpu.cpp index 91a01ae..2d7aeb0 100644 --- a/cpu.cpp +++ b/cpu.cpp @@ -52,118 +52,7 @@ static void pHexw(const unsigned short x) { -/* power */ -#define VCC sg->isegVCC -#define VSS sg->isegVSS - -/* inputs */ -#define CLK0 sg->isegCLK0 -#define IRQ sg->isegIRQ -#define RES sg->isegRES -#define NMI sg->isegNMI -#define RDY sg->isegRDY -#define SO sg->isegSO - -/* data bus (I/O) */ -#define DB0 sg->isegDB0 -#define DB1 sg->isegDB1 -#define DB3 sg->isegDB3 -#define DB2 sg->isegDB2 -#define DB5 sg->isegDB5 -#define DB4 sg->isegDB4 -#define DB7 sg->isegDB7 -#define DB6 sg->isegDB6 - -/* address bus (output) */ -#define AB0 sg->isegAB0 -#define AB1 sg->isegAB1 -#define AB2 sg->isegAB2 -#define AB3 sg->isegAB3 -#define AB4 sg->isegAB4 -#define AB5 sg->isegAB5 -#define AB6 sg->isegAB6 -#define AB7 sg->isegAB7 -#define AB8 sg->isegAB8 -#define AB9 sg->isegAB9 -#define AB12 sg->isegAB12 -#define AB13 sg->isegAB13 -#define AB10 sg->isegAB10 -#define AB11 sg->isegAB11 -#define AB14 sg->isegAB14 -#define AB15 sg->isegAB15 - -/* outputs */ -#define RW sg->isegRW -#define SYNC sg->isegSYNC -#define CLK1OUT sg->isegCLK1OUT -#define CLK2OUT sg->isegCLK2OUT - -/* internal registers */ -#define A0 sg->isegA0 -#define A1 sg->isegA1 -#define A2 sg->isegA2 -#define A3 sg->isegA3 -#define A4 sg->isegA4 -#define A5 sg->isegA5 -#define A6 sg->isegA6 -#define A7 sg->isegA7 - -#define X0 sg->isegX0 -#define X1 sg->isegX1 -#define X2 sg->isegX2 -#define X3 sg->isegX3 -#define X4 sg->isegX4 -#define X5 sg->isegX5 -#define X6 sg->isegX6 -#define X7 sg->isegX7 - -#define Y0 sg->isegY0 -#define Y1 sg->isegY1 -#define Y2 sg->isegY2 -#define Y3 sg->isegY3 -#define Y4 sg->isegY4 -#define Y5 sg->isegY5 -#define Y6 sg->isegY6 -#define Y7 sg->isegY7 - -#define PCL0 sg->isegPCL0 -#define PCL1 sg->isegPCL1 -#define PCL2 sg->isegPCL2 -#define PCL3 sg->isegPCL3 -#define PCL4 sg->isegPCL4 -#define PCL5 sg->isegPCL5 -#define PCL6 sg->isegPCL6 -#define PCL7 sg->isegPCL7 - -#define PCH0 sg->isegPCH0 -#define PCH1 sg->isegPCH1 -#define PCH2 sg->isegPCH2 -#define PCH3 sg->isegPCH3 -#define PCH4 sg->isegPCH4 -#define PCH5 sg->isegPCH5 -#define PCH6 sg->isegPCH6 -#define PCH7 sg->isegPCH7 - -#define P0 sg->isegP0 -#define P1 sg->isegP1 -#define P2 sg->isegP2 -#define P3 sg->isegP3 -#define P4 sg->isegP4 -#define P6 sg->isegP6 -#define P7 sg->isegP7 - -#define S0 sg->isegS0 -#define S1 sg->isegS1 -#define S2 sg->isegS2 -#define S3 sg->isegS3 -#define S4 sg->isegS4 -#define S5 sg->isegS5 -#define S6 sg->isegS6 -#define S7 sg->isegS7 - - - -static nodes* sg; +static nodes* n; static std::map map_i_seg; @@ -218,24 +107,21 @@ addressBus(addressBus) { } + n = new nodes(map_seg_i); - const int isegVSS = map_seg_i["-vss"]; - const int isegVCC = map_seg_i["-vcc"]; for (int i = 0; i != trns.size(); ++i) { trn& t = trns[i]; - if (t.c1 == isegVSS) { + if (t.c1 == n->VSS) { t.c1 = t.c2; - t.c2 = isegVSS; - } else if (t.c1 == isegVCC) { + t.c2 = n->VSS; + } else if (t.c1 == n->VCC) { t.c1 = t.c2; - t.c2 = isegVCC; + t.c2 = n->VCC; } segs[t.gate].gates.push_back(i); segs[t.c1].c1c2s.push_back(i); segs[t.c2].c1c2s.push_back(i); } - - sg = new nodes(map_seg_i); } CPU::~CPU() { @@ -259,7 +145,7 @@ void CPU::powerOn() { * temporary variable (see "step" method), we * need to initialize it here, to "phase one". */ - segs[CLK0].on = true; + segs[n->CLK0].on = true; @@ -274,18 +160,18 @@ void CPU::powerOn() { void CPU::initPins() { // set voltage supply and ground. - setSeg(VCC, true); - setSeg(VSS, false); + setSeg(n->VCC, true); + setSeg(n->VSS, false); // don't do the set-overflow overriding functionality - setSeg(SO, false); + setSeg(n->SO, false); // ready to run (i.e., do not do single-stepping of instructions) - setSeg(RDY, true); + setSeg(n->RDY, true); // pull up to indicate that we are not interrupting now - setSeg(IRQ, true); - setSeg(NMI, true); + setSeg(n->IRQ, true); + setSeg(n->NMI, true); /* @@ -299,12 +185,12 @@ void CPU::initPins() { * CPU does not start up normal operations yet. The caller can set RES_BAR high (by calling * reset) whenever he is ready to start the CPU running. */ - setSeg(RES, false); + setSeg(n->RES, false); } void CPU::reset() { - setSeg(RES, true); - recalc(RES); + setSeg(n->RES, true); + recalc(n->RES); } void CPU::tick() { @@ -323,13 +209,13 @@ void CPU::step() { * * The real 6502, of course, does not do this. */ - const bool nextPhase = !segs[CLK0].on; + const bool nextPhase = !segs[n->CLK0].on; - setSeg(CLK0, nextPhase); - recalc(CLK0); + setSeg(n->CLK0, nextPhase); + recalc(n->CLK0); // database read/write happens during Clock Phase 2 (only) - if (segs[CLK2OUT].on) { + if (segs[n->CLK2OUT].on) { rw(); } @@ -355,13 +241,13 @@ void CPU::rw() { void CPU::readBus() { - if (segs[RW].on) { + if (segs[n->RW].on) { setDataSegs(mRead(rAddr())); } } void CPU::writeBus() { - if (!segs[RW].on) { + if (!segs[n->RW].on) { mWrite(rAddr(), rData()); } } @@ -369,32 +255,32 @@ void CPU::writeBus() { void CPU::setDataSegs(const unsigned char data) { unsigned char x = data; - setSeg(DB0, x & 1); + setSeg(n->DB0, x & 1); x >>= 1; - setSeg(DB1, x & 1); + setSeg(n->DB1, x & 1); x >>= 1; - setSeg(DB2, x & 1); + setSeg(n->DB2, x & 1); x >>= 1; - setSeg(DB3, x & 1); + setSeg(n->DB3, x & 1); x >>= 1; - setSeg(DB4, x & 1); + setSeg(n->DB4, x & 1); x >>= 1; - setSeg(DB5, x & 1); + setSeg(n->DB5, x & 1); x >>= 1; - setSeg(DB6, x & 1); + setSeg(n->DB6, x & 1); x >>= 1; - setSeg(DB7, x & 1); + setSeg(n->DB7, x & 1); } void CPU::addDataToRecalc(std::set& s) { - s.insert(DB0); - s.insert(DB1); - s.insert(DB2); - s.insert(DB3); - s.insert(DB4); - s.insert(DB5); - s.insert(DB6); - s.insert(DB7); + s.insert(n->DB0); + s.insert(n->DB1); + s.insert(n->DB2); + s.insert(n->DB3); + s.insert(n->DB4); + s.insert(n->DB5); + s.insert(n->DB6); + s.insert(n->DB7); } unsigned char CPU::mRead(unsigned short addr) { @@ -438,31 +324,31 @@ void CPU::setSeg(const int iSeg, const bool up) { unsigned char CPU::rData() { - return readByte(DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0); + return readByte(n->DB7, n->DB6, n->DB5, n->DB4, n->DB3, n->DB2, n->DB1, n->DB0); } unsigned short CPU::rAddr() { - return readWord(AB15, AB14, AB13, AB12, AB11, AB10, AB9, AB8, AB7, AB6, AB5, AB4, AB3, AB2, AB1, AB0); + return readWord(n->AB15, n->AB14, n->AB13, n->AB12, n->AB11, n->AB10, n->AB9, n->AB8, n->AB7, n->AB6, n->AB5, n->AB4, n->AB3, n->AB2, n->AB1, n->AB0); } unsigned char CPU::rA() { - return readByte(A7, A6, A5, A4, A3, A2, A1, A0); + return readByte(n->A7, n->A6, n->A5, n->A4, n->A3, n->A2, n->A1, n->A0); } unsigned char CPU::rX() { - return readByte(X7, X6, X5, X4, X3, X2, X1, X0); + return readByte(n->X7, n->X6, n->X5, n->X4, n->X3, n->X2, n->X1, n->X0); } unsigned char CPU::rY() { - return readByte(Y7, Y6, Y5, Y4, Y3, Y2, Y1, Y0); + return readByte(n->Y7, n->Y6, n->Y5, n->Y4, n->Y3, n->Y2, n->Y1, n->Y0); } unsigned char CPU::rS() { - return readByte(S7, S6, S5, S4, S3, S2, S1, S0); + return readByte(n->S7, n->S6, n->S5, n->S4, n->S3, n->S2, n->S1, n->S0); } unsigned short CPU::rPC() { - return readWord(PCH7, PCH6, PCH5, PCH4, PCH3, PCH2, PCH1, PCH0, PCL7, PCL6, PCL5, PCL4, PCL3, PCL2, PCL1, PCL0); + return readWord(n->PCH7, n->PCH6, n->PCH5, n->PCH4, n->PCH3, n->PCH2, n->PCH1, n->PCH0, n->PCL7, n->PCL6, n->PCL5, n->PCL4, n->PCL3, n->PCL2, n->PCL1, n->PCL0); } @@ -555,7 +441,7 @@ void CPU::recalc(const std::set& riSeg) { * to riSegChanged. */ void CPU::recalcNode(const int iSeg, std::set& riSegChanged) { - if (!(iSeg == VCC || iSeg == VSS)) { + if (!(iSeg == n->VCC || iSeg == n->VSS)) { std::set riSegGroup; addToGroup(iSeg, riSegGroup); const bool groupOn = getGroupValue(riSegGroup); @@ -581,7 +467,7 @@ void CPU::setTrans(trn& t, const bool on, std::set& riSeg) { } void CPU::addRecalc(const int iSeg, std::set& riSeg) { - if (!(iSeg == VCC || iSeg == VSS)) { + if (!(iSeg == n->VCC || iSeg == n->VSS)) { riSeg.insert(iSeg); } } @@ -595,7 +481,7 @@ void CPU::addToGroup(int iSeg, std::set& riSeg) { if (!ret.second) { return; } - if (iSeg == VCC || iSeg == VSS) { + if (iSeg == n->VCC || iSeg == n->VSS) { return; } @@ -628,11 +514,11 @@ void CPU::addToGroup(int iSeg, std::set& riSeg) { */ bool CPU::getGroupValue(const std::set& riSeg) { /* If group contains ground, it's OFF, */ - if (riSeg.find(VSS) != riSeg.end()) { + if (riSeg.find(n->VSS) != riSeg.end()) { return false; } /* otherwise, if group contains voltage supply, it's ON. */ - else if (riSeg.find(VCC) != riSeg.end()) { + else if (riSeg.find(n->VCC) != riSeg.end()) { return true; } @@ -691,30 +577,30 @@ void CPU::dumpRegisters() { std::cout << " Y"; pHex(rY()); std::cout << " "; - std::cout << (segs[P7].on ? "N" : "n"); - std::cout << (segs[P6].on ? "V" : "v"); + std::cout << (segs[n->P7].on ? "N" : "n"); + std::cout << (segs[n->P6].on ? "V" : "v"); std::cout << "."; - std::cout << (segs[P4].on ? "B" : "b"); - std::cout << (segs[P3].on ? "D" : "d"); - std::cout << (segs[P2].on ? "I" : "i"); - std::cout << (segs[P1].on ? "Z" : "z"); - std::cout << (segs[P0].on ? "C" : "c"); + std::cout << (segs[n->P4].on ? "B" : "b"); + std::cout << (segs[n->P3].on ? "D" : "d"); + std::cout << (segs[n->P2].on ? "I" : "i"); + std::cout << (segs[n->P1].on ? "Z" : "z"); + std::cout << (segs[n->P0].on ? "C" : "c"); std::cout << " S"; pHex(rS()); std::cout << " PC"; pHexw(rPC()); - if (segs[CLK1OUT].on) { + if (segs[n->CLK1OUT].on) { std::cout << " PH1 "; } - if (segs[CLK2OUT].on) { + if (segs[n->CLK2OUT].on) { std::cout << " PH2"; - if (segs[RW].on) { + if (segs[n->RW].on) { std::cout << " R"; } else { std::cout << " W"; } } - if (!(segs[CLK1OUT].on || segs[CLK2OUT].on)) { + if (!(segs[n->CLK1OUT].on || segs[n->CLK2OUT].on)) { std::cout << " PH- "; } std::cout << " DB"; diff --git a/nodes.cpp b/nodes.cpp index 5d779c8..0a46446 100644 --- a/nodes.cpp +++ b/nodes.cpp @@ -4,112 +4,112 @@ nodes::nodes(std::map& map_seg_i) { /* power */ - isegVCC = map_seg_i["+vcc"]; - isegVSS = map_seg_i["-vss"]; + VCC = map_seg_i["+vcc"]; + VSS = map_seg_i["-vss"]; /* inputs */ - isegCLK0 = map_seg_i["-clk0"]; - isegIRQ = map_seg_i["-irq"]; - isegRES = map_seg_i["-res"]; - isegNMI = map_seg_i["-nmi"]; - isegRDY = map_seg_i["+rdy"]; - isegSO = map_seg_i["+s0"]; + CLK0 = map_seg_i["-clk0"]; + IRQ = map_seg_i["-irq"]; + RES = map_seg_i["-res"]; + NMI = map_seg_i["-nmi"]; + RDY = map_seg_i["+rdy"]; + SO = map_seg_i["+s0"]; /* data bus (I/O) */ - isegDB0 = map_seg_i["-db0"]; - isegDB1 = map_seg_i["-db1"]; - isegDB2 = map_seg_i["-db2"]; - isegDB3 = map_seg_i["-db3"]; - isegDB4 = map_seg_i["-db4"]; - isegDB5 = map_seg_i["-db5"]; - isegDB6 = map_seg_i["-db6"]; - isegDB7 = map_seg_i["-db7"]; + DB0 = map_seg_i["-db0"]; + DB1 = map_seg_i["-db1"]; + DB2 = map_seg_i["-db2"]; + DB3 = map_seg_i["-db3"]; + DB4 = map_seg_i["-db4"]; + DB5 = map_seg_i["-db5"]; + DB6 = map_seg_i["-db6"]; + DB7 = map_seg_i["-db7"]; /* address bus (output) */ - isegAB0 = map_seg_i["-ab0"]; - isegAB1 = map_seg_i["-ab1"]; - isegAB2 = map_seg_i["-ab2"]; - isegAB3 = map_seg_i["-ab3"]; - isegAB4 = map_seg_i["-ab4"]; - isegAB5 = map_seg_i["-ab5"]; - isegAB6 = map_seg_i["-ab6"]; - isegAB7 = map_seg_i["-ab7"]; - isegAB8 = map_seg_i["-ab8"]; - isegAB9 = map_seg_i["-ab9"]; - isegAB10 = map_seg_i["-ab10"]; - isegAB11 = map_seg_i["-ab11"]; - isegAB12 = map_seg_i["-ab12"]; - isegAB13 = map_seg_i["-ab13"]; - isegAB14 = map_seg_i["-ab14"]; - isegAB15 = map_seg_i["-ab15"]; + AB0 = map_seg_i["-ab0"]; + AB1 = map_seg_i["-ab1"]; + AB2 = map_seg_i["-ab2"]; + AB3 = map_seg_i["-ab3"]; + AB4 = map_seg_i["-ab4"]; + AB5 = map_seg_i["-ab5"]; + AB6 = map_seg_i["-ab6"]; + AB7 = map_seg_i["-ab7"]; + AB8 = map_seg_i["-ab8"]; + AB9 = map_seg_i["-ab9"]; + AB10 = map_seg_i["-ab10"]; + AB11 = map_seg_i["-ab11"]; + AB12 = map_seg_i["-ab12"]; + AB13 = map_seg_i["-ab13"]; + AB14 = map_seg_i["-ab14"]; + AB15 = map_seg_i["-ab15"]; /* outputs */ - isegRW = map_seg_i["-rw"]; - isegSYNC = map_seg_i["-sync"]; - isegCLK1OUT = map_seg_i["-clk1out"]; - isegCLK2OUT = map_seg_i["-clk2out"]; + RW = map_seg_i["-rw"]; + SYNC = map_seg_i["-sync"]; + CLK1OUT = map_seg_i["-clk1out"]; + CLK2OUT = map_seg_i["-clk2out"]; /* internal registers */ - isegA0 = map_seg_i["-a0"]; - isegA1 = map_seg_i["-a1"]; - isegA2 = map_seg_i["-a2"]; - isegA3 = map_seg_i["-a3"]; - isegA4 = map_seg_i["-a4"]; - isegA5 = map_seg_i["-a5"]; - isegA6 = map_seg_i["-a6"]; - isegA7 = map_seg_i["-a7"]; + A0 = map_seg_i["-a0"]; + A1 = map_seg_i["-a1"]; + A2 = map_seg_i["-a2"]; + A3 = map_seg_i["-a3"]; + A4 = map_seg_i["-a4"]; + A5 = map_seg_i["-a5"]; + A6 = map_seg_i["-a6"]; + A7 = map_seg_i["-a7"]; - isegX0 = map_seg_i["-x0"]; - isegX1 = map_seg_i["-x1"]; - isegX2 = map_seg_i["-x2"]; - isegX3 = map_seg_i["-x3"]; - isegX4 = map_seg_i["-x4"]; - isegX5 = map_seg_i["-x5"]; - isegX6 = map_seg_i["-x6"]; - isegX7 = map_seg_i["-x7"]; + X0 = map_seg_i["-x0"]; + X1 = map_seg_i["-x1"]; + X2 = map_seg_i["-x2"]; + X3 = map_seg_i["-x3"]; + X4 = map_seg_i["-x4"]; + X5 = map_seg_i["-x5"]; + X6 = map_seg_i["-x6"]; + X7 = map_seg_i["-x7"]; - isegY0 = map_seg_i["-y0"]; - isegY1 = map_seg_i["-y1"]; - isegY2 = map_seg_i["-y2"]; - isegY3 = map_seg_i["-y3"]; - isegY4 = map_seg_i["-y4"]; - isegY5 = map_seg_i["-y5"]; - isegY6 = map_seg_i["-y6"]; - isegY7 = map_seg_i["-y7"]; + Y0 = map_seg_i["-y0"]; + Y1 = map_seg_i["-y1"]; + Y2 = map_seg_i["-y2"]; + Y3 = map_seg_i["-y3"]; + Y4 = map_seg_i["-y4"]; + Y5 = map_seg_i["-y5"]; + Y6 = map_seg_i["-y6"]; + Y7 = map_seg_i["-y7"]; - isegPCL0 = map_seg_i["-pcl0"]; - isegPCL1 = map_seg_i["-pcl1"]; - isegPCL2 = map_seg_i["-pcl2"]; - isegPCL3 = map_seg_i["-pcl3"]; - isegPCL4 = map_seg_i["-pcl4"]; - isegPCL5 = map_seg_i["-pcl5"]; - isegPCL6 = map_seg_i["-pcl6"]; - isegPCL7 = map_seg_i["-pcl7"]; + PCL0 = map_seg_i["-pcl0"]; + PCL1 = map_seg_i["-pcl1"]; + PCL2 = map_seg_i["-pcl2"]; + PCL3 = map_seg_i["-pcl3"]; + PCL4 = map_seg_i["-pcl4"]; + PCL5 = map_seg_i["-pcl5"]; + PCL6 = map_seg_i["-pcl6"]; + PCL7 = map_seg_i["-pcl7"]; - isegPCH0 = map_seg_i["-pch0"]; - isegPCH1 = map_seg_i["-pch1"]; - isegPCH2 = map_seg_i["-pch2"]; - isegPCH3 = map_seg_i["-pch3"]; - isegPCH4 = map_seg_i["-pch4"]; - isegPCH5 = map_seg_i["-pch5"]; - isegPCH6 = map_seg_i["-pch6"]; - isegPCH7 = map_seg_i["-pch7"]; + PCH0 = map_seg_i["-pch0"]; + PCH1 = map_seg_i["-pch1"]; + PCH2 = map_seg_i["-pch2"]; + PCH3 = map_seg_i["-pch3"]; + PCH4 = map_seg_i["-pch4"]; + PCH5 = map_seg_i["-pch5"]; + PCH6 = map_seg_i["-pch6"]; + PCH7 = map_seg_i["-pch7"]; - isegP0 = map_seg_i["+Pout0"]; - isegP1 = map_seg_i["+Pout1"]; - isegP2 = map_seg_i["+Pout2"]; - isegP3 = map_seg_i["+Pout3"]; - isegP4 = map_seg_i["+Pout4"]; + P0 = map_seg_i["+Pout0"]; + P1 = map_seg_i["+Pout1"]; + P2 = map_seg_i["+Pout2"]; + P3 = map_seg_i["+Pout3"]; + P4 = map_seg_i["+Pout4"]; // P5 does not exist in the 6502 chip - isegP6 = map_seg_i["+Pout6"]; - isegP7 = map_seg_i["+Pout7"]; + P6 = map_seg_i["+Pout6"]; + P7 = map_seg_i["+Pout7"]; - isegS0 = map_seg_i["-s0"]; - isegS1 = map_seg_i["-s1"]; - isegS2 = map_seg_i["-s2"]; - isegS3 = map_seg_i["-s3"]; - isegS4 = map_seg_i["-s4"]; - isegS5 = map_seg_i["-s5"]; - isegS6 = map_seg_i["-s6"]; - isegS7 = map_seg_i["-s7"]; + S0 = map_seg_i["-s0"]; + S1 = map_seg_i["-s1"]; + S2 = map_seg_i["-s2"]; + S3 = map_seg_i["-s3"]; + S4 = map_seg_i["-s4"]; + S5 = map_seg_i["-s5"]; + S6 = map_seg_i["-s6"]; + S7 = map_seg_i["-s7"]; } diff --git a/nodes.h b/nodes.h index 3b75ab8..fd31538 100644 --- a/nodes.h +++ b/nodes.h @@ -7,113 +7,113 @@ class nodes { public: /* power */ - int isegVCC; - int isegVSS; + int VCC; + int VSS; /* inputs */ - int isegCLK0; - int isegIRQ; - int isegRES; - int isegNMI; - int isegRDY; - int isegSO; + int CLK0; + int IRQ; + int RES; + int NMI; + int RDY; + int SO; /* data bus; */ - int isegDB0; - int isegDB1; - int isegDB3; - int isegDB2; - int isegDB5; - int isegDB4; - int isegDB7; - int isegDB6; + int DB0; + int DB1; + int DB3; + int DB2; + int DB5; + int DB4; + int DB7; + int DB6; /* address bus; */ - int isegAB0; - int isegAB1; - int isegAB2; - int isegAB3; - int isegAB4; - int isegAB5; - int isegAB6; - int isegAB7; - int isegAB8; - int isegAB9; - int isegAB12; - int isegAB13; - int isegAB10; - int isegAB11; - int isegAB14; - int isegAB15; + int AB0; + int AB1; + int AB2; + int AB3; + int AB4; + int AB5; + int AB6; + int AB7; + int AB8; + int AB9; + int AB12; + int AB13; + int AB10; + int AB11; + int AB14; + int AB15; /* outputs */ - int isegRW; - int isegSYNC; - int isegCLK1OUT; - int isegCLK2OUT; + int RW; + int SYNC; + int CLK1OUT; + int CLK2OUT; /* internal registers */ - int isegA0; - int isegA1; - int isegA2; - int isegA3; - int isegA4; - int isegA5; - int isegA6; - int isegA7; + int A0; + int A1; + int A2; + int A3; + int A4; + int A5; + int A6; + int A7; - int isegX0; - int isegX1; - int isegX2; - int isegX3; - int isegX4; - int isegX5; - int isegX6; - int isegX7; + int X0; + int X1; + int X2; + int X3; + int X4; + int X5; + int X6; + int X7; - int isegY0; - int isegY1; - int isegY2; - int isegY3; - int isegY4; - int isegY5; - int isegY6; - int isegY7; + int Y0; + int Y1; + int Y2; + int Y3; + int Y4; + int Y5; + int Y6; + int Y7; - int isegPCL0; - int isegPCL1; - int isegPCL2; - int isegPCL3; - int isegPCL4; - int isegPCL5; - int isegPCL6; - int isegPCL7; + int PCL0; + int PCL1; + int PCL2; + int PCL3; + int PCL4; + int PCL5; + int PCL6; + int PCL7; - int isegPCH0; - int isegPCH1; - int isegPCH2; - int isegPCH3; - int isegPCH4; - int isegPCH5; - int isegPCH6; - int isegPCH7; + int PCH0; + int PCH1; + int PCH2; + int PCH3; + int PCH4; + int PCH5; + int PCH6; + int PCH7; - int isegP0; - int isegP1; - int isegP2; - int isegP3; - int isegP4; - int isegP6; - int isegP7; + int P0; + int P1; + int P2; + int P3; + int P4; + int P6; + int P7; - int isegS0; - int isegS1; - int isegS2; - int isegS3; - int isegS4; - int isegS5; - int isegS6; - int isegS7; + int S0; + int S1; + int S2; + int S3; + int S4; + int S5; + int S6; + int S7; nodes(std::map& map_seg_i); };